watch.tan.qmsg

做的跑马车程序 连上硬件可显示 下了绝对有用

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "cp2 sel\[6\] selsig\[6\] 17.000 ns register " "Info: Minimum tco from clock cp2 to destination pin sel\[6\] through register selsig\[6\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns + Shortest register " "Info: + Shortest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns selsig\[6\] 3 REG LC59 2 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'selsig\[6\]'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] selsig[6] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] selsig[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns selsig\[6\] 1 REG LC59 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'selsig\[6\]'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { selsig[6] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns sel\[6\] 2 PIN PIN_35 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'sel\[6\]'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } }  } 0}  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] selsig[6] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset n 24.000 ns Shortest " "Info: Shortest tpd from source pin reset to destination pin n is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns reset 1 PIN PIN_1 10 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 10; PIN Node = 'reset'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { reset } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns process1~43 2 COMB LC79 2 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC79; Fanout = 2; COMB Node = 'process1~43'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { reset process1~43 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns n\$latch~10 3 COMB LC11 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC11; Fanout = 3; COMB Node = 'n\$latch~10'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { process1~43 n$latch~10 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns n 4 PIN PIN_8 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'n'" {  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { n$latch~10 n } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 87.50 % " "Info: Total cell delay = 21.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 12.50 % " "Info: Total interconnect delay = 3.000 ns ( 12.50 % )" {  } {  } 0}  } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "24.000 ns" { reset process1~43 n$latch~10 n } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 05 23:39:40 2006 " "Info: Processing ended: Sun Nov 05 23:39:40 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}