📄 watch.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cp1 " "Info: Detected ripple clock cp1 as buffer" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "cp1" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "count\[10\] " "Info: Detected ripple clock count\[10\] as buffer" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } { "e:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "count\[10\]" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cp2 register num2\[3\] register num\[3\] 71.43 MHz 14.0 ns Internal " "Info: Clock cp2 has Internal fmax of 71.43 MHz between source register num2\[3\] and destination register num\[3\] (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num2\[3\] 1 REG LC80 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC80; Fanout = 32; REG Node = 'num2\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { num2[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns num~4311 2 COMB LC67 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC67; Fanout = 1; COMB Node = 'num~4311'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { num2[3] num~4311 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns num\[3\] 3 REG LC68 23 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC68; Fanout = 23; REG Node = 'num\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { num~4311 num[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { num2[3] num~4311 num[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num\[3\] 3 REG LC68 23 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC68; Fanout = 23; REG Node = 'num\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] num[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns - Longest register " "Info: - Longest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cp1 2 REG LC60 25 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC60; Fanout = 25; REG Node = 'cp1'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 cp1 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num2\[3\] 3 REG LC80 32 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC80; Fanout = 32; REG Node = 'num2\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { cp1 num2[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num2[3] } "NODE_NAME" } } } } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num2[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { num2[3] num~4311 num[3] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num2[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "num4\[3\] beginstop cp2 2.000 ns register " "Info: tsu for register num4\[3\] (data pin = beginstop, clock pin = cp2) is 2.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns beginstop 1 PIN PIN_84 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 43; PIN Node = 'beginstop'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { beginstop } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns num4\[3\] 2 REG LC42 23 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC42; Fanout = 23; REG Node = 'num4\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "7.000 ns" { beginstop num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num4[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns - Shortest register " "Info: - Shortest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cp1 2 REG LC60 25 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC60; Fanout = 25; REG Node = 'cp1'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 cp1 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num4\[3\] 3 REG LC42 23 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC42; Fanout = 23; REG Node = 'num4\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { cp1 num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num4[3] } "NODE_NAME" } } } } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num4[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp2 seg\[1\] num\[0\] 44.000 ns register " "Info: tco from clock cp2 to destination pin seg\[1\] through register num\[0\] is 44.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns + Longest register " "Info: + Longest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num\[0\] 3 REG LC82 26 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC82; Fanout = 26; REG Node = 'num\[0\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] num[0] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "31.000 ns + Longest register pin " "Info: + Longest register to pin delay is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[0\] 1 REG LC82 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC82; Fanout = 26; REG Node = 'num\[0\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { num[0] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 81 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns process2~458 2 COMB LC87 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC87; Fanout = 1; COMB Node = 'process2~458'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { num[0] process2~458 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 18.000 ns segsig\[1\]\$d_and~74 3 COMB LC101 2 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 18.000 ns; Loc. = LC101; Fanout = 2; COMB Node = 'segsig\[1\]\$d_and~74'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { process2~458 segsig[1]$d_and~74 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 27.000 ns segsig\[1\]~90 4 COMB LC8 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 27.000 ns; Loc. = LC8; Fanout = 3; COMB Node = 'segsig\[1\]~90'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { segsig[1]$d_and~74 segsig[1]~90 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 79 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 31.000 ns seg\[1\] 5 PIN PIN_9 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 31.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'seg\[1\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { segsig[1]~90 seg[1] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.000 ns 80.65 % " "Info: Total cell delay = 25.000 ns ( 80.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 19.35 % " "Info: Total interconnect delay = 6.000 ns ( 19.35 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "31.000 ns" { num[0] process2~458 segsig[1]$d_and~74 segsig[1]~90 seg[1] } "NODE_NAME" } } } } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[0] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "31.000 ns" { num[0] process2~458 segsig[1]$d_and~74 segsig[1]~90 seg[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "beginstop n 24.000 ns Longest " "Info: Longest tpd from source pin beginstop to destination pin n is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns beginstop 1 PIN PIN_84 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 43; PIN Node = 'beginstop'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { beginstop } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns process1~43 2 COMB LC79 2 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC79; Fanout = 2; COMB Node = 'process1~43'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { beginstop process1~43 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns n\$latch~10 3 COMB LC11 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC11; Fanout = 3; COMB Node = 'n\$latch~10'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { process1~43 n$latch~10 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns n 4 PIN PIN_8 0 " "Info: 4: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'n'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { n$latch~10 n } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 87.50 % " "Info: Total cell delay = 21.000 ns ( 87.50 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 12.50 % " "Info: Total interconnect delay = 3.000 ns ( 12.50 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "24.000 ns" { beginstop process1~43 n$latch~10 n } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "num4\[3\] beginstop cp2 6.000 ns register " "Info: th for register num4\[3\] (data pin = beginstop, clock pin = cp2) is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns + Longest register " "Info: + Longest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cp1 2 REG LC60 25 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC60; Fanout = 25; REG Node = 'cp1'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 cp1 } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 30 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num4\[3\] 3 REG LC42 23 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC42; Fanout = 23; REG Node = 'num4\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { cp1 num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num4[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns beginstop 1 PIN PIN_84 43 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 43; PIN Node = 'beginstop'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "" { beginstop } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns num4\[3\] 2 REG LC42 23 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC42; Fanout = 23; REG Node = 'num4\[3\]'" { } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "7.000 ns" { beginstop num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num4[3] } "NODE_NAME" } } } } 0} } { { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num4[3] } "NODE_NAME" } } } { "E:/大三上/yw/db/watch_cmp.qrpt" "" "" { Report "E:/大三上/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/大三上/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num4[3] } "NODE_NAME" } } } } 0}
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