watch.map.qmsg

做的跑马车程序 连上硬件可显示 下了绝对有用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 05 23:39:27 2006 " "Info: Processing started: Sun Nov 05 23:39:27 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off watch -c watch " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off watch -c watch" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file watch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watch-behave " "Info: Found design unit 1: watch-behave" {  } { { "E:/大三上/yw/watch.vhd" "watch-behave" "" { Text "E:/大三上/yw/watch.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 watch " "Info: Found entity 1: watch" {  } { { "E:/大三上/yw/watch.vhd" "watch" "" { Text "E:/大三上/yw/watch.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count watch.vhd(36) " "Warning: VHDL Process Statement warning at watch.vhd(36): signal count is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset watch.vhd(40) " "Warning: VHDL Process Statement warning at watch.vhd(40): signal reset is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num4 watch.vhd(64) " "Warning: VHDL Process Statement warning at watch.vhd(64): signal num4 is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 64 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "beginstop watch.vhd(72) " "Warning: VHDL Process Statement warning at watch.vhd(72): signal beginstop is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 72 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "n watch.vhd(38) " "Warning: VHDL Process Statement warning at watch.vhd(38): signal or variable n may not be assigned a new value in every possible path through the Process Statement. Signal or variable n holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 38 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(97) " "Warning: VHDL Process Statement warning at watch.vhd(97): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 97 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(99) " "Warning: VHDL Process Statement warning at watch.vhd(99): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(101) " "Warning: VHDL Process Statement warning at watch.vhd(101): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(103) " "Warning: VHDL Process Statement warning at watch.vhd(103): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(105) " "Warning: VHDL Process Statement warning at watch.vhd(105): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(107) " "Warning: VHDL Process Statement warning at watch.vhd(107): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(109) " "Warning: VHDL Process Statement warning at watch.vhd(109): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(111) " "Warning: VHDL Process Statement warning at watch.vhd(111): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(113) " "Warning: VHDL Process Statement warning at watch.vhd(113): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 113 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(115) " "Warning: VHDL Process Statement warning at watch.vhd(115): signal num is in statement, but is not in sensitivity list" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "segsig watch.vhd(79) " "Warning: VHDL Process Statement warning at watch.vhd(79): signal or variable segsig may not be assigned a new value in every possible path through the Process Statement. Signal or variable segsig holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 79 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "e:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "e:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "e:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "e:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "e:/altera/quartus41/libraries/megafunctions/look_add.tdf" "look_add" "" { Text "e:/altera/quartus41/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "e:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "e:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "13 " "Info: Ignored 13 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "13 " "Info: Ignored 13 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "n~1 " "Warning: Node n~1" {  } { { "E:/大三上/yw/watch.vhd" "" "" { Text "E:/大三上/yw/watch.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "cp2 " "Info: Promoted clock signal driven by pin cp2 to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "108 " "Info: Implemented 108 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "85 " "Info: Implemented 85 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "5 " "Info: Implemented 5 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 05 23:39:32 2006 " "Info: Processing ended: Sun Nov 05 23:39:32 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}