📄 watch.map.rpt
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Analysis & Synthesis report for watch
Sun Nov 05 23:39:32 2006
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. Analysis & Synthesis Resource Utilization by Entity
6. Analysis & Synthesis Equations
7. Analysis & Synthesis Source Files Read
8. Analysis & Synthesis Resource Usage Summary
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Nov 05 23:39:32 2006 ;
; Quartus II Version ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name ; watch ;
; Top-level Entity Name ; watch ;
; Family ; MAX7000S ;
; Total macrocells ; 85 ;
; Total pins ; 18 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Family name ; MAX7000S ; Stratix ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; watch ; watch ;
; State Machine Processing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
+----------------------------------------------------------------------+-----------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
watch
|-- lpm_add_sub:add_rtl_0
|-- addcore:adder
|-- addcore:adder[0]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- addcore:adder[1]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- look_add:look_ahead_unit
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |watch ; 85 ; 18 ; |watch ;
+----------------------------+------------+------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/大三上/yw/watch.map.eqn.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+-------------------------------------------------------------+-----------------+
; watch.vhd ; yes ;
; e:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf ; yes ;
; e:/altera/quartus41/libraries/megafunctions/addcore.inc ; yes ;
; e:/altera/quartus41/libraries/megafunctions/look_add.inc ; yes ;
; e:/altera/quartus41/libraries/megafunctions/addcore.tdf ; yes ;
; e:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf ; yes ;
; e:/altera/quartus41/libraries/megafunctions/look_add.tdf ; yes ;
; e:/altera/quartus41/libraries/megafunctions/altshift.tdf ; yes ;
+-------------------------------------------------------------+-----------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 85 ;
; Total registers ; 51 ;
; I/O pins ; 18 ;
; Shareable expanders ; 5 ;
; Parallel expanders ; 4 ;
; Maximum fan-out node ; beginstop ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 827 ;
; Average fan-out ; 7.66 ;
+----------------------+----------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sun Nov 05 23:39:27 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off watch -c watch
Info: Found 2 design units, including 1 entities, in source file watch.vhd
Info: Found design unit 1: watch-behave
Info: Found entity 1: watch
Warning: VHDL Process Statement warning at watch.vhd(36): signal count is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(40): signal reset is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(64): signal num4 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(72): signal beginstop is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(38): signal or variable n may not be assigned a new value in every possible path through the Process Statement. Signal or variable n holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at watch.vhd(97): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(99): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(101): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(103): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(105): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(107): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(109): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(111): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(113): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(115): signal num is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at watch.vhd(79): signal or variable segsig may not be assigned a new value in every possible path through the Process Statement. Signal or variable segsig holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 13 buffer(s)
Info: Ignored 13 SOFT buffer(s)
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Node n~1
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin cp2 to global clock signal
Info: Implemented 108 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 14 output pins
Info: Implemented 1 bidirectional pins
Info: Implemented 85 macrocells
Info: Implemented 5 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
Info: Processing ended: Sun Nov 05 23:39:32 2006
Info: Elapsed time: 00:00:05
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