📄 avrnet.lss
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8c6: 82 e0 ldi r24, 0x02 ; 2
8c8: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
waitspi();
8cc: 6a e1 ldi r22, 0x1A ; 26
8ce: 83 e0 ldi r24, 0x03 ; 3
8d0: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
while(length)
{
length--;
8d4: ce 01 movw r24, r28
8d6: 8c 5d subi r24, 0xDC ; 220
8d8: 68 2f mov r22, r24
8da: 86 e0 ldi r24, 0x06 ; 6
8dc: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
// write data
8e0: cc 5d subi r28, 0xDC ; 220
8e2: d5 4e sbci r29, 0xE5 ; 229
8e4: 6d 2f mov r22, r29
8e6: 77 27 eor r23, r23
8e8: c4 52 subi r28, 0x24 ; 36
8ea: da 41 sbci r29, 0x1A ; 26
8ec: 87 e0 ldi r24, 0x07 ; 7
8ee: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
SPDR = *buffer++;
waitspi();
}
8f2: 40 e0 ldi r20, 0x00 ; 0
8f4: 60 e0 ldi r22, 0x00 ; 0
8f6: 8a e7 ldi r24, 0x7A ; 122
8f8: 0e 94 d3 03 call 0x7a6 ; 0x7a6 <enc28j60WriteOp>
CSPASSIVE;
8fc: c4 98 cbi 0x18, 4 ; 24
// send the contents of the transmit buffer onto the network
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
8fe: 8a e7 ldi r24, 0x7A ; 122
900: 8f b9 out 0x0f, r24 ; 15
902: 77 99 sbic 0x0e, 7 ; 14
904: 09 c0 rjmp .+18 ; 0x918 <enc28j60_packet_send+0x60>
906: fd cf rjmp .-6 ; 0x902 <enc28j60_packet_send+0x4a>
// Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
if( (enc28j60Read(EIR) & EIR_TXERIF) )
{
908: 21 97 sbiw r28, 0x01 ; 1
enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
}
90a: f8 01 movw r30, r16
90c: 80 81 ld r24, Z
90e: 8f b9 out 0x0f, r24 ; 15
}
910: 77 9b sbis 0x0e, 7 ; 14
912: fe cf rjmp .-4 ; 0x910 <enc28j60_packet_send+0x58>
914: 0f 5f subi r16, 0xFF ; 255
916: 1f 4f sbci r17, 0xFF ; 255
918: 20 97 sbiw r28, 0x00 ; 0
91a: b1 f7 brne .-20 ; 0x908 <enc28j60_packet_send+0x50>
//*******************************************************************************************
//
91c: c4 9a sbi 0x18, 4 ; 24
// Function : enc28j60_mac_is_linked
// Description : return MAC link status.
//
91e: 48 e0 ldi r20, 0x08 ; 8
920: 6f e1 ldi r22, 0x1F ; 31
922: 80 e8 ldi r24, 0x80 ; 128
924: 0e 94 d3 03 call 0x7a6 ; 0x7a6 <enc28j60WriteOp>
//*******************************************************************************************
/*
BYTE enc28j60_mac_is_linked(void)
928: 8c e1 ldi r24, 0x1C ; 28
92a: 0e 94 02 04 call 0x804 ; 0x804 <enc28j60Read>
92e: 81 ff sbrs r24, 1
930: 05 c0 rjmp .+10 ; 0x93c <enc28j60_packet_send+0x84>
{
if ( (enc28j60_read_phyreg(PHSTAT1) & PHSTAT1_LLSTAT ) )
932: 48 e0 ldi r20, 0x08 ; 8
934: 6f e1 ldi r22, 0x1F ; 31
936: 80 ea ldi r24, 0xA0 ; 160
938: 0e 94 d3 03 call 0x7a6 ; 0x7a6 <enc28j60WriteOp>
93c: df 91 pop r29
93e: cf 91 pop r28
940: 1f 91 pop r17
942: 0f 91 pop r16
944: 08 95 ret
00000946 <enc28j60_packet_receive>:
return 1;
else
return 0;
}
*/
//*******************************************************************************************
//
// Function : enc28j60_packet_receive
// Description : check received packet and return length of data
//
//*******************************************************************************************
//WORD data_length;
WORD enc28j60_packet_receive ( BYTE *rxtx_buffer, WORD max_length )
{
WORD_BYTES rx_status, data_length;
// check if a packet has been received and buffered
// if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
// The above does not work. See Rev. B4 Silicon Errata point 6.
if( enc28j60Read(EPKTCNT) == 0 )
{
return 0;
}
// Set the read pointer to the start of the received packet
enc28j60Write(ERDPTL, next_packet_ptr.bytes[0]);
946: bf 92 push r11
948: cf 92 push r12
94a: df 92 push r13
94c: ef 92 push r14
94e: ff 92 push r15
950: 0f 93 push r16
952: 1f 93 push r17
954: cf 93 push r28
956: df 93 push r29
958: 6c 01 movw r12, r24
95a: 7b 01 movw r14, r22
enc28j60Write(ERDPTH, next_packet_ptr.bytes[1]);
// read the next packet pointer
next_packet_ptr.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
next_packet_ptr.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
95c: 89 e3 ldi r24, 0x39 ; 57
95e: 0e 94 02 04 call 0x804 ; 0x804 <enc28j60Read>
962: 88 23 and r24, r24
964: 19 f4 brne .+6 ; 0x96c <enc28j60_packet_receive+0x26>
966: 80 e0 ldi r24, 0x00 ; 0
968: 90 e0 ldi r25, 0x00 ; 0
96a: 5a c0 rjmp .+180 ; 0xa20 <enc28j60_packet_receive+0xda>
// read the packet length (see datasheet page 43)
data_length.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
data_length.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
data_length.word -=4; //remove the CRC count
// read the receive status (see datasheet page 43)
96c: 60 91 eb 00 lds r22, 0x00EB
970: 80 e0 ldi r24, 0x00 ; 0
972: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
rx_status.bytes[0] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
976: 60 91 ec 00 lds r22, 0x00EC
97a: 81 e0 ldi r24, 0x01 ; 1
97c: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
rx_status.bytes[1] = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
if ( data_length.word > (max_length-1) )
980: 60 e0 ldi r22, 0x00 ; 0
982: 8a e3 ldi r24, 0x3A ; 58
984: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
988: 80 93 eb 00 sts 0x00EB, r24
{
98c: 60 e0 ldi r22, 0x00 ; 0
98e: 8a e3 ldi r24, 0x3A ; 58
990: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
994: b8 2e mov r11, r24
996: 80 93 ec 00 sts 0x00EC, r24
data_length.word = max_length-1;
}
99a: 60 e0 ldi r22, 0x00 ; 0
99c: 8a e3 ldi r24, 0x3A ; 58
99e: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
9a2: c8 2f mov r28, r24
// check CRC and symbol errors (see datasheet page 44, table 7-3):
9a4: 60 e0 ldi r22, 0x00 ; 0
9a6: 8a e3 ldi r24, 0x3A ; 58
9a8: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
9ac: d8 2f mov r29, r24
// The ERXFCON.CRCEN is set by default. Normally we should not
9ae: 24 97 sbiw r28, 0x04 ; 4
// need to check this.
if ( (rx_status.word & 0x80)==0 )
{
9b0: 60 e0 ldi r22, 0x00 ; 0
9b2: 8a e3 ldi r24, 0x3A ; 58
9b4: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
9b8: 08 2f mov r16, r24
// invalid
9ba: 60 e0 ldi r22, 0x00 ; 0
9bc: 8a e3 ldi r24, 0x3A ; 58
9be: 0e 94 c0 03 call 0x780 ; 0x780 <enc28j60ReadOp>
data_length.word = 0;
}
9c2: b7 01 movw r22, r14
9c4: 61 50 subi r22, 0x01 ; 1
9c6: 70 40 sbci r23, 0x00 ; 0
9c8: 6c 17 cp r22, r28
9ca: 7d 07 cpc r23, r29
9cc: 08 f4 brcc .+2 ; 0x9d0 <enc28j60_packet_receive+0x8a>
else
{
9ce: eb 01 movw r28, r22
// read data from rx buffer and save to rxtx_buffer
rx_status.word = data_length.word;
CSACTIVE;
// issue read command
SPDR = ENC28J60_READ_BUF_MEM;
waitspi();
9d0: 07 fd sbrc r16, 7
9d2: 03 c0 rjmp .+6 ; 0x9da <enc28j60_packet_receive+0x94>
while(rx_status.word)
{
rx_status.word--;
9d4: c0 e0 ldi r28, 0x00 ; 0
9d6: d0 e0 ldi r29, 0x00 ; 0
9d8: 14 c0 rjmp .+40 ; 0xa02 <enc28j60_packet_receive+0xbc>
SPDR = 0x00;
waitspi();
*rxtx_buffer++ = SPDR;
}
CSPASSIVE;
9da: 9e 01 movw r18, r28
}
9dc: c4 98 cbi 0x18, 4 ; 24
// Move the RX read pointer to the start of the next received packet
9de: 8a e3 ldi r24, 0x3A ; 58
9e0: 8f b9 out 0x0f, r24 ; 15
// This frees the memory we just read out
9e2: 77 99 sbic 0x0e, 7 ; 14
9e4: 0a c0 rjmp .+20 ; 0x9fa <enc28j60_packet_receive+0xb4>
9e6: fd cf rjmp .-6 ; 0x9e2 <enc28j60_packet_receive+0x9c>
enc28j60Write(ERXRDPTL, next_packet_ptr.bytes[0]);
enc28j60Write(ERXRDPTH, next_packet_ptr.bytes[1]);
// decrement the packet counter indicate we are done with this packet
9e8: 1f b8 out 0x0f, r1 ; 15
enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
9ea: 77 9b sbis 0x0e, 7 ; 14
9ec: fe cf rjmp .-4 ; 0x9ea <enc28j60_packet_receive+0xa4>
9ee: 8f b1 in r24, 0x0f ; 15
9f0: f6 01 movw r30, r12
9f2: 81 93 st Z+, r24
9f4: 6f 01 movw r12, r30
9f6: 21 50 subi r18, 0x01 ; 1
9f8: 30 40 sbci r19, 0x00 ; 0
9fa: 21 15 cp r18, r1
9fc: 31 05 cpc r19, r1
9fe: a1 f7 brne .-24 ; 0x9e8 <enc28j60_packet_receive+0xa2>
return( data_length.word );
}
a00: c4 9a sbi 0x18, 4 ; 24
a02: 60 91 eb 00 lds r22, 0x00EB
a06: 8c e0 ldi r24, 0x0C ; 12
a08: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
a0c: 6b 2d mov r22, r11
a0e: 8d e0 ldi r24, 0x0D ; 13
a10: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
a14: 40 e4 ldi r20, 0x40 ; 64
a16: 6e e1 ldi r22, 0x1E ; 30
a18: 80 e8 ldi r24, 0x80 ; 128
a1a: 0e 94 d3 03 call 0x7a6 ; 0x7a6 <enc28j60WriteOp>
a1e: ce 01 movw r24, r28
a20: df 91 pop r29
a22: cf 91 pop r28
a24: 1f 91 pop r17
a26: 0f 91 pop r16
a28: ff 90 pop r15
a2a: ef 90 pop r14
a2c: df 90 pop r13
a2e: cf 90 pop r12
a30: bf 90 pop r11
a32: 08 95 ret
00000a34 <enc28j60_init>:
a34: ef 92 push r14
a36: ff 92 push r15
a38: 0f 93 push r16
a3a: 1f 93 push r17
a3c: 7c 01 movw r14, r24
a3e: 8b 9a sbi 0x11, 3 ; 17
a40: 8a 98 cbi 0x11, 2 ; 17
a42: 92 9a sbi 0x12, 2 ; 18
a44: 93 98 cbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a46: 80 e4 ldi r24, 0x40 ; 64
a48: 9c e9 ldi r25, 0x9C ; 156
a4a: 01 97 sbiw r24, 0x01 ; 1
a4c: f1 f7 brne .-4 ; 0xa4a <enc28j60_init+0x16>
a4e: 93 9a sbi 0x12, 3 ; 18
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a50: 00 e0 ldi r16, 0x00 ; 0
a52: 10 e0 ldi r17, 0x00 ; 0
a54: c8 01 movw r24, r16
a56: 01 97 sbiw r24, 0x01 ; 1
a58: f1 f7 brne .-4 ; 0xa56 <enc28j60_init+0x22>
a5a: 87 b3 in r24, 0x17 ; 23
a5c: 80 6b ori r24, 0xB0 ; 176
a5e: 87 bb out 0x17, r24 ; 23
a60: c4 9a sbi 0x18, 4 ; 24
a62: 88 b3 in r24, 0x18 ; 24
a64: 8f 75 andi r24, 0x5F ; 95
a66: 88 bb out 0x18, r24 ; 24
a68: 80 e5 ldi r24, 0x50 ; 80
a6a: 8d b9 out 0x0d, r24 ; 13
a6c: 70 9a sbi 0x0e, 0 ; 14
a6e: 4f ef ldi r20, 0xFF ; 255
a70: 60 e0 ldi r22, 0x00 ; 0
a72: 8f ef ldi r24, 0xFF ; 255
a74: 0e 94 d3 03 call 0x7a6 ; 0x7a6 <enc28j60WriteOp>
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
a78: c8 01 movw r24, r16
a7a: 01 97 sbiw r24, 0x01 ; 1
a7c: f1 f7 brne .-4 ; 0xa7a <enc28j60_init+0x46>
a7e: 10 92 ec 00 sts 0x00EC, r1
a82: 10 92 eb 00 sts 0x00EB, r1
a86: 60 e0 ldi r22, 0x00 ; 0
a88: 88 e0 ldi r24, 0x08 ; 8
a8a: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
a8e: 60 e0 ldi r22, 0x00 ; 0
a90: 89 e0 ldi r24, 0x09 ; 9
a92: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
a96: 60 e0 ldi r22, 0x00 ; 0
a98: 8c e0 ldi r24, 0x0C ; 12
a9a: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
a9e: 60 e0 ldi r22, 0x00 ; 0
aa0: 8d e0 ldi r24, 0x0D ; 13
aa2: 0e 94 0d 04 call 0x81a ; 0x81a <enc28j60Write>
aa6: 63 e2 ldi r22, 0x23 ; 35
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