📄 sys_init.asm
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.include x24x_app.h
.def SYS_INIT
.bss GPR0,1
.bss adc_sel,1
stack_start .usect "stack",32
T1_period_ .set 0bb8h
T2_period_ .set 0bb8h
wd_rst_1 .set 055h ; watchdog timer reset string
wd_rst_2 .set 0aah ; watchdog timer reset string
********************************************************************
** System configuration **
********************************************************************
SYS_INIT:
DINT
lacl #0
lar ar1,#0a000h
mar *,ar1
lacl #0
rpt #255
sacl *+
; ------------------------------------------------------------------
; Configure system registers
; ------------------------------------------------------------------
LDP #0E0h ; point at Sys Mod reg page 0
SPLK #0100000011000000b,SYSCR ; Make CPUCLK src of CLKOUT
; 5432109876543210
* bits 15-14 01: No action (1x/x0-software reset)
* bits 13-8 0-0: Reserved
* bits 7-6 11: CLKOUT source is CPUCLK (00-I/O, 01-WDCLK, 10-SYSCLK)
* bits 5-0 0-0: Reserved
SPLK #0000000000100000b,SYSSR ; Clear all SYSSR bits (except HP0)
; 5432109876543210
* bit 15 0: Power on reset status bit (0-no,1-yes)
* bits 14-13 00: Reserved
* bit 12 0: Illegal address status (0-no,1-yes)
* bit 11 0: Reserved
* bit 10 0: Software reset status (0-no, 1-yes)
* bit 9 0: WD reset status (0-no, 1-yes)
* bits 8-6 000: Reserved
* bit 5 (HP0) 1: VCC on reset/override (0-Normal,1-Enable FLASH programming)
* bit 4 0: Reserved
* bit 3 0: Analog VCC out-of-regulation (0-no, 1-yes)
* bits 2-1 00: Reserved
* bit 0 0: System interrupt vector pending (0-no, 1-pending)
SPLK #01101111b,WD_CNTL ; Disable the WD timer
SPLK #wd_rst_1,WD_KEY ; Reset watchdog timer
SPLK #wd_rst_2,WD_KEY
SPLK #0000000010110001b,CKCR1 ; CPUCLK=20MHz if CLKIN=10MHz
; 5432109876543210
* bits 15-8 0-0h: don't care
* bits 7-4 1011: freq of CLKIN is 10MHz (0000-32MHz,1111-2MHz)
* bit 3 0: PLL input prescaler is x/1, (1-x/2)
* bits 2-0 000: PLL output multiple is 1, (000-1,001-2 100-5, 101-9)
SPLK #0000000000000001b,CKCR0 ; Disable and re-enable to activate change
; 5432109876543210 ;0x0001
PLL_test SPLK #0000000011000001b,CKCR0 ; Wait until PLL is re-enabled.
; 5432109876543210 ;0x00f1
* bits 15-8 00h: don't care
* bits 7-6 11: PLL enabled (mode,00-CLKIN/2,01-CKKIN,10/11-PLL)
* bits 5-4 00: Clock mode indication bits (1x-PLL working)
* bits 3-2 00: Low power mode 0 selected
* bit 1 0: ACLK disabled
* bit 0 1: System clock prescaler is x/2 (0-x/4)
; BIT CKCR0,BIT5 ; Bits 5,4 are 1x when PLL is working
; BCND PLL_test,NTC ; Branch to PLL_test if PLL is not locked
;The DAC module requires that wait states be generated for proper ;operation.
LDP #GPR0 ; Point to memory page 0 of B1
SPLK #04,GPR0 ; Set wait state generator
;Program Space, 0 wait states
;Data Space, 0 wait states
;I/O Space, 1 wait state
OUT GPR0,0ffffh ; WSGR <= (GPR0)
LDP #0E1h ; Point at Sys Module reg page 1
; Configure all I/O pins to I/O function pins
; to carry out the required power inverter reset
; sequence.
SPLK #0000101100001111b,OCRA ; 180f
; 5432109876543210
* bit 15 0: 0-IOPB7, 1-TMRCLK
* bit 14 0: 0-IOPB6, 1-TMRDIR
* bit 13 0: 0-IOPB5, 1-T3PWM/T3CMPR
* bit 12 0: 0-IOPB4, 1-T2PWM/T2CMPR
* bit 11 1: 0-IOPB3, 1-T1PWM/T1CMPR
* bit 10 1: 0-IOPB2, 1-PWM9/CMP9
* bit 9 1: 0-IOPB1, 1-PWM8/CMP8
* bit 8 1: 0-IOPB0, 1-PWM7/CMP7
* bits 7-4 0-0: Reserved
* bit 3 1: 0-IOPA3, 1-ADCIN8
* bit 2 1: 0-IOPA2, 1-ADCIN9
* bit 1 1: 0-IOPA1, 1-ADCIN1
* bit 0 1: 0-IOPA0, 1-ADCIN0
SPLK #0000000000000000b,OCRB
; 5432109876543210
* bits 15-8 0-0: Reserved
* bit 7 0: 0-IOPC7, 1-CAP4
* bit 6 0: 0-IOPC6, 1-CAP3
* bit 5 0: 0-IOPC5, 1-CAP2/QEP2
* bit 4 0: 0-IOPC4, 1-CAP1/QEP1
* bit 3 0: 0-BIO_, 1-IOPC3
* bit 2 0: 0-XF, 1-IOPC2
* bit 1 0: Don't care
* bit 0 0: 0-IOPC0, 1-ADCSOC
SPLK #0000000000000000b,PADATDIR ;A3,A2=Out, A1,A0=In, A3,A2=1,1
; 5432109876543210
* bits 15-12 0-0: Reserved
* bit 11 0: 0-IOPA3 is input, 1-IOPA3 is output
* bit 10 0: 0-IOPA2 is input, 1-IOPA2 is output
* bit 9 0: 0-IOPA1 is input, 1-IOPA1 is output
* bit 8 0: 0-IOPA0 is input, 1-IOPA0 is output
* bits 7-4 0-0: Reserved
* bit 3 0: IOPA3 data
* bit 2 0: IOPA2 data
* bit 1 0: IOPA1 data
* bit 0 0: IOPA0 data
SPLK #0001110000000000b,PBDATDIR ; Config Port B, IOB7 is DriveEnable
; 5432109876543210
* bits 15 0: 0-IOPB7 is input, 1-IOPB7 is output
* bits 14 0: 0-IOPB6 is input, 1-IOPB6 is output
* bits 13 0: 0-IOPB5 is input, 1-IOPB5 is output T3PWM/IOPB5 INT2
* bits 12 1: 0-IOPB4 is input, 1-IOPB4 is output T2PWM CONVST2
* bits 11 1: 0-IOPB3 is input, 1-IOPB3 is output T1PWM CONVST1
* bits 10 1: 0-IOPB2 is input, 1-IOPB2 is output PWM9/IOPB2 INT1
* bits 9 0: 0-IOPB1 is input, 1-IOPB1 is output PWM8
* bits 8 0: 0-IOPB0 is input, 1-IOPB0 is output PWM7
* bits 7 0: 0-IOPB7 low 1-IOPB7 high
* bits 6 0: 0-IOPB6 low 1-IOPB6 high
* bits 5 0: 0-IOPB5 low 1-IOPB5 high
* bits 4 1: 0-IOPB4 low 1-IOPB4 high
* bits 3 0: 0-IOPB3 low 1-IOPB3 high
* bits 2 1: 0-IOPB2 low 1-IOPB2 high
* bits 1 0: 0-IOPB1 low 1-IOPB1 high
* bits 0 0: 0-IOPB0 low 1-IOPB0 high
SPLK #0000000000000000b,PCDATDIR ; Config Port C, IOPC6 is DriveEnable
; 5432109876543210
* bits 15-8 10-0: 0-IOPCx is input, 1-IOPCx is output
* bits 7-0 0-0: IOPC data
;
;-------------------------------------------------------------
;Initialize peripherals
;-------------------------------------------------------------
; CLRC XF
;WAIT1 BCND LOOP1,BIO
; B WAIT1
LOOP1 LDP #adc_sel
SPLK #000ch,adc_sel
; SPLK #0000h,adc_sel
out adc_sel,00000h ;I/O SPACE ADDRESS 0X0000 AS CS0
;A0=1,A1=1,A2=1,A3=0,A4~A15 IS RESERVED
;4 CHANNEL IS SELECTED
;EXADC2 INITIALIZATION
;WAIT2 BCND LOOP2,BIO
; B WAIT2
LOOP2
OUT adc_sel,00001h ;I/O SPACE ADDRESS 0X0001 AS CS1
;A0=1,A1=1,A2=1,A3=0,A4~A15 IS RESERVED
;4 CHANNEL IS SELECTED
; OUT adc_sel,00002h ;
SETC XF
;-----------------------------------------------------------------------
; Initialize Event Manager
;-----------------------------------------------------------------------
;----------------------------------------------------------------------
; Configure GP Timers
;----------------------------------------------------------------------
LDP #232 ; Point at EV register page
; Clear all Event Manager registers before proceeding further.
SPLK #0,T1CON
SPLK #0,T2CON
SPLK #0,T3CON
SPLK #0,DBTCON
SPLK #0,COMCON
SPLK #0,CAPCON
SPLK #0,T1CNT
SPLK #0,T2CNT
SPLK #0,T3CNT
; Configure GP Timer 1, the PWM time base
SPLK #T1_period_,T1PER ; Init GP Timer 1 period
; Configure GP Timer 2, the sampling and control time base
SPLK #T1_period_,T2PER ; Init GP Timer 2 period
; Configure GP Timer 3
SPLK #T1_period_,T3PER ; Init GP Timer 3 period
;Kill all F. Comp/PWM outputs.
; SPLK #T1_period_,CMPR1
; SPLK #T1_period_,CMPR2
; SPLK #T1_period_,CMPR3
SPLK #0100h,CMPR1
SPLK #0100h,CMPR2
SPLK #0100h,CMPR3
; SPLK #02e4h,SCMPR1
SPLK #0AB4H,SCMPR1
; SPLK #03A4h,SCMPR2
SPLK #0B74H,SCMPR2
; SPLK #02dah,SCMPR3
SPLK #0AAAH,SCMPR3
; SPLK #10e0h,DBTCON ;Define dead band (16*50=0.8us)
; 5432109876543210
; SPLK #20e0h,DBTCON ;Define dead band (32*50=1.6us)
; SPLK #40e0h,DBTCON ;Define dead band (64*50=3.2us)
; SPLK #28e0h,DBTCON ;Define dead band (40*50=2.0us)
;Let GP Timer compare outputs toggle (to have more things I can
;look at with an oscilloscope).
;SPLK #02dah,T1CMP ;>=0X01F4 is high level, 0x0000 is low
SPLK #0AAAh,T1CMP
;SPLK #01e4h,T2CMP
SPLK #09B4h,T2CMP
;SPLK #01e4h,T3CMP
SPLK #09B4h,T3CMP
SPLK #0000100110011001b,ACTR ;Full Action Cntl
; 5432109876543210
* bits 15 0: Dir = CCW (n/c)
* bits 14-12 000: D2D1D0 = 000 (n/c)
* bits 11-10 10: PWM6/CMP6 active high
* bits 9-8 01: PWM5/CMP5 active low
* bits 7-6 10: PWM4/CMP4 active high
* bits 5-4 01: PWM3/CMP3 active low
* bits 3-2 01: PWM2/CMP2 active high
* bits 1-0 01: PWM1/CMP1 active low
; SPLK #0000111111111111b,ACTR
SPLK #0000000000101010b,SACTR ;Full Action Cntl
; 5432109876543210
* bits 15-6 Reserved
* bits 5-4 10: PWM9/CMP9 active high
* bits 3-2 10: PWM8/CMP8 active high
* bits 1-0 10: PWM7/CMP7 active high
; Write COMCON twice to enable PWM outputs
SPLK #0000001100000111b,COMCON; Compare Cntl
SPLK #1000001100000111b,COMCON; Compare Cntl
; 5432109876543210
* bit 15 1: Enable Compare/PWM operation
* bits 14-13 00: Load F. Comp. Reg on UF of GPT1
* bit 12 0: Disable Space Vector PWM Mode
* bits 11-10 00: Load ACTR on underflow of GPt1
* bit 9 1: Enable F Compare outputs
* bit 8 1: Enable S Compare outputs
* bit 7 0: Select GP Timer 1 as time base for S Comp Units
* bits 6-5 00: Load SCMPR on Underflow of selected GP Timer
* bits 4-3 00: Load SACTR on underflow of selected GP Timer
* bit 2 1: F. Comp. Unit 3 in PWM mode
* PWM5/CMP5 & PWM6/CMP6 are PWM outputs
* bit 1 1: F. Comp. Unit 2 in PWM mode
* PWM3/CMP3 & PWM4/CMP4 are PWM outputs
* bit 0 1: F. Comp. Unit 1 in PWM mode
* PWM1/CMP1 & PWM2/CMP2 are PWM outputs
; Define GP Timer compare output polarities and actions
SPLK #0000000001010101b,GPTCON
; 5432109876543210
* bits 12-11 00: No GP Timer 3 event starts ADC
* bits 10-9 00: No GP Timer 2 event starts ADC
* bits 8-7 00: No GP Timer 1 event starts ADC
* bit 6 1: Enable GP Timer Compare outputs
* bits 5-4 01: GP Timer 3 comp output active low
* bits 3-2 01: GP Timer 2 comp output active low
* bits 1-0 01: GP Timer 1 comp output active low
SPLK #1001000001000010b,T1CON; Set GP Timer control register
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 010: continuous-up/down count mode
* bits 10-8 000: Prescaler = /1
* bit 7 0: Reserved
* bit 6 0: disable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: reserved
SPLK #1001000011000010b,T2CON; Set GP Timer 2 control
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 0: disable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use GP Timer 1 PR
; synch w GPT1
SPLK #1001000011000010b,T3CON ; GPT3 in c-up mode
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 0: disable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use Timer 1 PR
; p/s=32 in synch w T1
LDP #232 ; point at EV reg page
SPLK #0ffffh,IFRA ; Clear all Group A int flags
SPLK #0ffffh,IFRB ; Clear all Group B int flags
SPLK #0ffffh,IFRC ; Clear all Group C int flags
SPLK #0200h,IMRA ; Unmask PDPINT,GPT1 UF ints
SPLK #0h,IMRB ; Mask all EV Grp B ints
SPLK #0h,IMRC ; Mask all EV Grp C ints
LDP #0 ; Point at MMR page
SPLK #0000010b,IMR ; Enable int to CPU (no emu int)
SPLK #0ffffh,IFR ; Clear pending int to CPU
SETC OVM;Set overflow protect mode
SETC SXM ;Set sign extension (allow) mode
; -----------------------------------------------------------------
; Enable global interrupt to start real-time operation
; -----------------------------------------------------------------
LDP #232
; Enable global interrupt
SPLK #1001000001000010b,T1CON; Set GP Timer control register
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 010: continuous-up/down count mode
* bits 10-8 000: Prescaler = /1
* bit 7 0: Reserved
* bit 6 1: Enable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: reserved
SPLK #1001000011000010b,T2CON; Set GP Timer 2 control
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 1: Enable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use GP Timer 1 PR
; synch w GPT1
SPLK #1001000011000010b,T3CON ; GPT3 in c-up mode
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 1: Enable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use Timer 1 PR
; p/s=32 in synch w T1
EINT
RET
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