📄 sys_init.asm
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;===========================================================================
; File Name: Sys_init.asm
;
; Module Name: S Y S _ I N I T
;
;
;
; Description: Initializes F24x/xx devices
;
;
;=====================================================================================
.include x24x_app.h
.def SYS_INIT
.ref GPR0
.ref adc_sel
.bss mSEC,1 ; time to wait
.def wd_rst_1, wd_rst_2
stack_size .set 20h
stack_start .usect "stack",stack_size
; Timer 1 period which determines the PWM frequency.
T1_period_ .set 05dch
T2_period_ .set 05dch
T1_p .set 0010h
; Tp = 2*3125*50nS=315.2uS => Fp = 3.17KHz
********************************************************************
** System configuration **
********************************************************************
SYS_INIT:
DINT
;clear inter RAM locations from 300h to 3ffh
; lacl #0
; lar ar1,#300h
; mar *,ar1
; rpt #255
; sacl *+
;clear inter SRAM locations from 8000h to ffffh
lacl #0
lar ar1,#0a000h
mar *,ar1
lacl #0
rpt #255
sacl *+
; ------------------------------------------------------------------
; Configure system registers
; ------------------------------------------------------------------
LDP #0E0h ; point at Sys Mod reg page 0
SPLK #0100000011000000b,SYSCR ; Make CPUCLK src of CLKOUT
; 5432109876543210
* bits 15-14 01: No action (1x/x0-software reset)
* bits 13-8 0-0: Reserved
* bits 7-6 11: CLKOUT source is CPUCLK (00-I/O, 01-WDCLK, 10-SYSCLK)
* bits 5-0 0-0: Reserved
SPLK #0000000000100000b,SYSSR ; Clear all SYSSR bits (except HP0)
; 5432109876543210
* bit 15 0: Power on reset status bit (0-no,1-yes)
* bits 14-13 00: Reserved
* bit 12 0: Illegal address status (0-no,1-yes)
* bit 11 0: Reserved
* bit 10 0: Software reset status (0-no, 1-yes)
* bit 9 0: WD reset status (0-no, 1-yes)
* bits 8-6 000: Reserved
* bit 5 (HP0) 1: VCC on reset/override (0-Normal,1-Enable FLASH programming)
* bit 4 0: Reserved
* bit 3 0: Analog VCC out-of-regulation (0-no, 1-yes)
* bits 2-1 00: Reserved
* bit 0 0: System interrupt vector pending (0-no, 1-pending)
SPLK #01101111b,WD_CNTL ; Disable the WD timer
SPLK #wd_rst_1,WD_KEY ; Reset watchdog timer
SPLK #wd_rst_2,WD_KEY
SPLK #0000000010110001b,CKCR1 ; CPUCLK=20MHz if CLKIN=10MHz
; 5432109876543210
* bits 15-8 0-0h: don't care
* bits 7-4 1011: freq of CLKIN is 10MHz (0000-32MHz,1111-2MHz)
* bit 3 0: PLL input prescaler is x/1, (1-x/2)
* bits 2-0 000: PLL output multiple is 1, (000-1,001-2 100-5, 101-9)
; SPLK #10111011b,CKCR1 ; CPUCLK=20MHz if CLKIN=10MHz
; SPLK #11001100b,CKCR1 ; CPUCLK=20MHz if CLKIN=8MHz
; SPLK #11100100b,CKCR1 ; CPUCLK=20MHz if CLKIN=4MHz
SPLK #0000000000000001b,CKCR0 ; Disable and re-enable to activate change
; 5432109876543210 ;0x0001
PLL_test SPLK #0000000011000001b,CKCR0 ; Wait until PLL is re-enabled.
; 5432109876543210 ;0x00f1
* bits 15-8 00h: don't care
* bits 7-6 11: PLL enabled (mode,00-CLKIN/2,01-CKKIN,10/11-PLL)
* bits 5-4 00: Clock mode indication bits (1x-PLL working)
* bits 3-2 00: Low power mode 0 selected
* bit 1 0: ACLK disabled
* bit 0 1: System clock prescaler is x/2 (0-x/4)
; BIT CKCR0,BIT5 ; Bits 5,4 are 1x when PLL is working
; BCND PLL_test,NTC ; Branch to PLL_test if PLL is not locked
;The DAC module requires that wait states be generated for proper ;operation.
LDP #GPR0 ; Point to memory page 0 of B1
SPLK #04,GPR0 ; Set wait state generator
;Program Space, 0 wait states
;Data Space, 0 wait states
;I/O Space, 1 wait state
OUT GPR0,0ffffh ; WSGR <= (GPR0)
LDP #0E1h ; Point at Sys Module reg page 1
; Configure all I/O pins to I/O function pins
; to carry out the required power inverter reset
; sequence.
SPLK #0000101100001111b,OCRA ; 180f
; 5432109876543210
* bit 15 0: 0-IOPB7, 1-TMRCLK
* bit 14 0: 0-IOPB6, 1-TMRDIR
* bit 13 0: 0-IOPB5, 1-T3PWM/T3CMPR
* bit 12 0: 0-IOPB4, 1-T2PWM/T2CMPR
* bit 11 1: 0-IOPB3, 1-T1PWM/T1CMPR
* bit 10 1: 0-IOPB2, 1-PWM9/CMP9
* bit 9 1: 0-IOPB1, 1-PWM8/CMP8
* bit 8 1: 0-IOPB0, 1-PWM7/CMP7
* bits 7-4 0-0: Reserved
* bit 3 1: 0-IOPA3, 1-ADCIN8
* bit 2 1: 0-IOPA2, 1-ADCIN9
* bit 1 1: 0-IOPA1, 1-ADCIN1
* bit 0 1: 0-IOPA0, 1-ADCIN0
SPLK #0000000011111000b,OCRB
; 5432109876543210
* bits 15-8 0-0: Reserved
* bit 7 0: 0-IOPC7, 1-CAP4
* bit 6 0: 0-IOPC6, 1-CAP3
* bit 5 0: 0-IOPC5, 1-CAP2/QEP2
* bit 4 0: 0-IOPC4, 1-CAP1/QEP1
* bit 3 0: 0-BIO_, 1-IOPC3
* bit 2 0: 0-XF, 1-IOPC2
* bit 1 0: Don't care
* bit 0 0: 0-IOPC0, 1-ADCSOC
SPLK #0000000000000000b,PADATDIR ;A3,A2=Out, A1,A0=In, A3,A2=1,1
; 5432109876543210
* bits 15-12 0-0: Reserved
* bit 11 0: 0-IOPA3 is input, 1-IOPA3 is output
* bit 10 0: 0-IOPA2 is input, 1-IOPA2 is output
* bit 9 0: 0-IOPA1 is input, 1-IOPA1 is output
* bit 8 0: 0-IOPA0 is input, 1-IOPA0 is output
* bits 7-4 0-0: Reserved
* bit 3 0: IOPA3 data
* bit 2 0: IOPA2 data
* bit 1 0: IOPA1 data
* bit 0 0: IOPA0 data
SPLK #0001110000010000b,PBDATDIR ; Config Port B, IOB7 is DriveEnable
; 5432109876543210
* bits 15 0: 0-IOPB7 is input, 1-IOPB7 is output
* bits 14 0: 0-IOPB6 is input, 1-IOPB6 is output
* bits 13 0: 0-IOPB5 is input, 1-IOPB5 is output T3PWM/IOPB5 INT2
* bits 12 1: 0-IOPB4 is input, 1-IOPB4 is output T2PWM CONVST2
* bits 11 1: 0-IOPB3 is input, 1-IOPB3 is output T1PWM CONVST1
* bits 10 1: 0-IOPB2 is input, 1-IOPB2 is output PWM9/IOPB2 INT1
* bits 9 0: 0-IOPB1 is input, 1-IOPB1 is output PWM8
* bits 8 0: 0-IOPB0 is input, 1-IOPB0 is output PWM7
* bits 7 0: 0-IOPB7 low 1-IOPB7 high
* bits 6 0: 0-IOPB6 low 1-IOPB6 high
* bits 5 0: 0-IOPB5 low 1-IOPB5 high
* bits 4 1: 0-IOPB4 low 1-IOPB4 high
* bits 3 0: 0-IOPB3 low 1-IOPB3 high
* bits 2 1: 0-IOPB2 low 1-IOPB2 high
* bits 1 0: 0-IOPB1 low 1-IOPB1 high
* bits 0 0: 0-IOPB0 low 1-IOPB0 high
SPLK #0000000000000000b,PCDATDIR ; Config Port C, IOPC6 is DriveEnable
; 5432109876543210
* bits 15-8 10-0: 0-IOPCx is input, 1-IOPCx is output
* bits 7-0 0-0: IOPC data
;
;-------------------------------------------------------------
;Initialize peripherals
;-------------------------------------------------------------
;----------------------------------------------------------------------
; Initialize and start ADC module
;----------------------------------------------------------------------
LDP #0E0h ; Point at Sys Module reg page 0
SPLK #0000000000000011b,ADC_CNTL2 ; Disable EV and Ext
SPLK #0101100111111111b,ADC_CNTL1
;SOC and set p/s
lacl ADCFIFO2 ; Clear ADC result FIFOs
lacl ADCFIFO2
lacl ADCFIFO1
lacl ADCFIFO1
;--------------------------------------------------------------------
;Initialized off-chip ADCs
;--------------------------------------------------------------------
;=======================================
;HAD MODIFIED BY LIU HAO
LOOP1 LDP #adc_sel
SPLK #000ch,adc_sel
; SPLK #0000h,adc_sel
out adc_sel,00000h ;I/O SPACE ADDRESS 0X0000 AS CS0
;A0=1,A1=1,A2=1,A3=0,A4~A15 IS RESERVED
;4 CHANNEL IS SELECTED
;EXADC2 INITIALIZATION
NOP
NOP
NOP
LOOP2
OUT adc_sel,00001h ;I/O SPACE ADDRESS 0X0001 AS CS1
;A0=1,A1=1,A2=1,A3=0,A4~A15 IS RESERVED
;4 CHANNEL IS SELECTED
; OUT adc_sel,00002h ;
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