📄 mc9s12hz256.h
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byte :1;
byte :1;
byte RDPE :1; /* Reduced Drive of Port E */
byte :1;
byte :1;
byte RDPK :1; /* Reduced Drive of Port K */
} Bits;
struct {
byte grpRDPx :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} RDRIVSTR;
extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);
#define RDRIV _RDRIV.Byte
#define RDRIV_RDPA _RDRIV.Bits.RDPA
#define RDRIV_RDPB _RDRIV.Bits.RDPB
#define RDRIV_RDPE _RDRIV.Bits.RDPE
#define RDRIV_RDPK _RDRIV.Bits.RDPK
#define RDRIV_RDPx _RDRIV.MergedBits.grpRDPx
#define RDRIV_RDPA_MASK 1
#define RDRIV_RDPB_MASK 2
#define RDRIV_RDPE_MASK 16
#define RDRIV_RDPK_MASK 128
#define RDRIV_RDPx_MASK 3
#define RDRIV_RDPx_BITNUM 0
/*** EBICTL - External Bus Interface Control; 0x0000000E ***/
typedef union {
byte Byte;
struct {
byte ESTR :1; /* E Stretches */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} EBICTLSTR;
extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);
#define EBICTL _EBICTL.Byte
#define EBICTL_ESTR _EBICTL.Bits.ESTR
#define EBICTL_ESTR_MASK 1
/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/
typedef union {
byte Byte;
struct {
byte RAMHAL :1; /* Internal RAM map alignment */
byte :1;
byte :1;
byte RAM11 :1; /* Internal RAM map position Bit 11 */
byte RAM12 :1; /* Internal RAM map position Bit 12 */
byte RAM13 :1; /* Internal RAM map position Bit 13 */
byte RAM14 :1; /* Internal RAM map position Bit 14 */
byte RAM15 :1; /* Internal RAM map position Bit 15 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte grpRAM_11 :5;
} MergedBits;
} INITRMSTR;
extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);
#define INITRM _INITRM.Byte
#define INITRM_RAMHAL _INITRM.Bits.RAMHAL
#define INITRM_RAM11 _INITRM.Bits.RAM11
#define INITRM_RAM12 _INITRM.Bits.RAM12
#define INITRM_RAM13 _INITRM.Bits.RAM13
#define INITRM_RAM14 _INITRM.Bits.RAM14
#define INITRM_RAM15 _INITRM.Bits.RAM15
#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11
#define INITRM_RAM INITRM_RAM_11
#define INITRM_RAMHAL_MASK 1
#define INITRM_RAM11_MASK 8
#define INITRM_RAM12_MASK 16
#define INITRM_RAM13_MASK 32
#define INITRM_RAM14_MASK 64
#define INITRM_RAM15_MASK 128
#define INITRM_RAM_11_MASK 248
#define INITRM_RAM_11_BITNUM 3
/*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte REG11 :1; /* Internal Registers Map Position Bit 11 */
byte REG12 :1; /* Internal Registers Map Position Bit 12 */
byte REG13 :1; /* Internal Registers Map Position Bit 13 */
byte REG14 :1; /* Internal Registers Map Position Bit 14 */
byte :1;
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte grpREG_11 :4;
byte :1;
} MergedBits;
} INITRGSTR;
extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);
#define INITRG _INITRG.Byte
#define INITRG_REG11 _INITRG.Bits.REG11
#define INITRG_REG12 _INITRG.Bits.REG12
#define INITRG_REG13 _INITRG.Bits.REG13
#define INITRG_REG14 _INITRG.Bits.REG14
#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11
#define INITRG_REG INITRG_REG_11
#define INITRG_REG11_MASK 8
#define INITRG_REG12_MASK 16
#define INITRG_REG13_MASK 32
#define INITRG_REG14_MASK 64
#define INITRG_REG_11_MASK 120
#define INITRG_REG_11_BITNUM 3
/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/
typedef union {
byte Byte;
struct {
byte EEON :1; /* Internal EEPROM On */
byte :1;
byte :1;
byte EE11 :1; /* Internal EEPROM map position Bit 11 */
byte EE12 :1; /* Internal EEPROM map position Bit 12 */
byte EE13 :1; /* Internal EEPROM map position Bit 13 */
byte EE14 :1; /* Internal EEPROM map position Bit 14 */
byte EE15 :1; /* Internal EEPROM map position Bit 15 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte grpEE_11 :5;
} MergedBits;
} INITEESTR;
extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);
#define INITEE _INITEE.Byte
#define INITEE_EEON _INITEE.Bits.EEON
#define INITEE_EE11 _INITEE.Bits.EE11
#define INITEE_EE12 _INITEE.Bits.EE12
#define INITEE_EE13 _INITEE.Bits.EE13
#define INITEE_EE14 _INITEE.Bits.EE14
#define INITEE_EE15 _INITEE.Bits.EE15
#define INITEE_EE_11 _INITEE.MergedBits.grpEE_11
#define INITEE_EE INITEE_EE_11
#define INITEE_EEON_MASK 1
#define INITEE_EE11_MASK 8
#define INITEE_EE12_MASK 16
#define INITEE_EE13_MASK 32
#define INITEE_EE14_MASK 64
#define INITEE_EE15_MASK 128
#define INITEE_EE_11_MASK 248
#define INITEE_EE_11_BITNUM 3
/*** MISC - Miscellaneous System Control Register; 0x00000013 ***/
typedef union {
byte Byte;
struct {
byte ROMON :1; /* Enable Flash EEPROM */
byte ROMHM :1; /* Flash EEPROM only in second half of memory map */
byte EXSTR0 :1; /* External Access Stretch Bit 0 */
byte EXSTR1 :1; /* External Access Stretch Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte :1;
byte :1;
byte grpEXSTR :2;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} MISCSTR;
extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013);
#define MISC _MISC.Byte
#define MISC_ROMON _MISC.Bits.ROMON
#define MISC_ROMHM _MISC.Bits.ROMHM
#define MISC_EXSTR0 _MISC.Bits.EXSTR0
#define MISC_EXSTR1 _MISC.Bits.EXSTR1
#define MISC_EXSTR _MISC.MergedBits.grpEXSTR
#define MISC_ROMON_MASK 1
#define MISC_ROMHM_MASK 2
#define MISC_EXSTR0_MASK 4
#define MISC_EXSTR1_MASK 8
#define MISC_EXSTR_MASK 12
#define MISC_EXSTR_BITNUM 2
/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/
typedef union {
byte Byte;
struct {
byte ADR0 :1; /* Test register select Bit 0 */
byte ADR1 :1; /* Test register select Bit 1 */
byte ADR2 :1; /* Test register select Bit 2 */
byte ADR3 :1; /* Test register select Bit 3 */
byte WRTINT :1; /* Write to the Interrupt Test Registers */
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpADR :4;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} ITCRSTR;
extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);
#define ITCR _ITCR.Byte
#define ITCR_ADR0 _ITCR.Bits.ADR0
#define ITCR_ADR1 _ITCR.Bits.ADR1
#define ITCR_ADR2 _ITCR.Bits.ADR2
#define ITCR_ADR3 _ITCR.Bits.ADR3
#define ITCR_WRTINT _ITCR.Bits.WRTINT
#define ITCR_ADR _ITCR.MergedBits.grpADR
#define ITCR_ADR0_MASK 1
#define ITCR_ADR1_MASK 2
#define ITCR_ADR2_MASK 4
#define ITCR_ADR3_MASK 8
#define ITCR_WRTINT_MASK 16
#define ITCR_ADR_MASK 15
#define ITCR_ADR_BITNUM 0
/*** ITEST - Interrupt Test Register; 0x00000016 ***/
typedef union {
byte Byte;
struct {
byte INT0 :1; /* Interrupt Test Register Bit 0 */
byte INT2 :1; /* Interrupt Test Register Bit 1 */
byte INT4 :1; /* Interrupt Test Register Bit 2 */
byte INT6 :1; /* Interrupt Test Register Bit 3 */
byte INT8 :1; /* Interrupt Test Register Bit 4 */
byte INTA :1; /* Interrupt Test Register Bit 5 */
byte INTC :1; /* Interrupt Test Register Bit 6 */
byte INTE :1; /* Interrupt Test Register Bit 7 */
} Bits;
} ITESTSTR;
extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);
#define ITEST _ITEST.Byte
#define ITEST_INT0 _ITEST.Bits.INT0
#define ITEST_INT2 _ITEST.Bits.INT2
#define ITEST_INT4 _ITEST.Bits.INT4
#define ITEST_INT6 _ITEST.Bits.INT6
#define ITEST_INT8 _ITEST.Bits.INT8
#define ITEST_INTA _ITEST.Bits.INTA
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