mc9s12hz256.c

Demo HZ256 Cluster LCD2 CW31 SH v1 ICD

volatile PWMSCLASTR _PWMSCLA;                              /* PWM Scale A Register */
volatile PWMSCLBSTR _PWMSCLB;                              /* PWM Scale B Register */
volatile PWMSDNSTR _PWMSDN;                                /* PWM Shutdown Register */
volatile RDRADSTR _RDRAD;                                  /* Port AD Reduced Drive Register */
volatile RDRIVSTR _RDRIV;                                  /* Reduced Drive of I/O Lines */
volatile RDRLSTR _RDRL;                                    /* Port L Reduced Drive Register */
volatile RDRMSTR _RDRM;                                    /* Port M Reduced Drive Register */
volatile RDRPSTR _RDRP;                                    /* Port P Reduced Drive Register */
volatile RDRSSTR _RDRS;                                    /* Port S Reduced Drive Register */
volatile RDRTSTR _RDRT;                                    /* Port T Reduced Drive Register */
volatile REFDVSTR _REFDV;                                  /* CRG Reference Divider Register */
volatile RTICTLSTR _RTICTL;                                /* CRG RTI Control Register */
volatile RTZ0CTLSTR _RTZ0CTL;                              /* SSD 0 Return to Zero Control register */
volatile RTZ1CTLSTR _RTZ1CTL;                              /* SSD 1 Return to Zero Control register */
volatile RTZ2CTLSTR _RTZ2CTL;                              /* SSD 2 Return to Zero Control register */
volatile RTZ3CTLSTR _RTZ3CTL;                              /* SSD 3 Return to Zero Control register */
volatile SCI0CR1STR _SCI0CR1;                              /* SCI 0 Control Register 1 */
volatile SCI0CR2STR _SCI0CR2;                              /* SCI 0 Control Register 2 */
volatile SCI0DRHSTR _SCI0DRH;                              /* SCI 0 Data Register High */
volatile SCI0DRLSTR _SCI0DRL;                              /* SCI 0 Data Register Low */
volatile SCI0SR1STR _SCI0SR1;                              /* SCI 0 Status Register 1 */
volatile SCI0SR2STR _SCI0SR2;                              /* SCI 0 Status Register 2 */
volatile SCI1CR1STR _SCI1CR1;                              /* SCI 1 Control Register 1 */
volatile SCI1CR2STR _SCI1CR2;                              /* SCI 1 Control Register 2 */
volatile SCI1DRHSTR _SCI1DRH;                              /* SCI 1 Data Register High */
volatile SCI1DRLSTR _SCI1DRL;                              /* SCI 1 Data Register Low */
volatile SCI1SR1STR _SCI1SR1;                              /* SCI 1 Status Register 1 */
volatile SCI1SR2STR _SCI1SR2;                              /* SCI 1 Status Register 2 */
volatile SPIBRSTR _SPIBR;                                  /* SPI 0 Baud Rate Register */
volatile SPICR1STR _SPICR1;                                /* SPI 0 Control Register */
volatile SPICR2STR _SPICR2;                                /* SPI 0 Control Register 2 */
volatile SPIDRSTR _SPIDR;                                  /* SPI 0 Data Register */
volatile SPISRSTR _SPISR;                                  /* SPI 0 Status Register */
volatile SRRUSTR _SRRU;                                    /* Port U Slew Rate Register */
volatile SRRVSTR _SRRV;                                    /* Port V Reduced Drive Register */
volatile SSD0CTLSTR _SSD0CTL;                              /* SSD 0 Stepper Stall Detector Control register */
volatile SSD0FLGSTR _SSD0FLG;                              /* SSD 0 Stepper Stall Detector Flag register */
volatile SSD1CTLSTR _SSD1CTL;                              /* SSD 1 Stepper Stall Detector Control register */
volatile SSD1FLGSTR _SSD1FLG;                              /* SSD 1 Stepper Stall Detector Flag register */
volatile SSD2CTLSTR _SSD2CTL;                              /* SSD 2 Stepper Stall Detector Control register */
volatile SSD2FLGSTR _SSD2FLG;                              /* SSD 2 Stepper Stall Detector Flag register */
volatile SSD3CTLSTR _SSD3CTL;                              /* SSD 3 Stepper Stall Detector Control register */
volatile SSD3FLGSTR _SSD3FLG;                              /* SSD 3 Stepper Stall Detector Flag register */
volatile SYNRSTR _SYNR;                                    /* CRG Synthesizer Register */
volatile TCTL1STR _TCTL1;                                  /* Timer Control Register 1 */
volatile TCTL2STR _TCTL2;                                  /* Timer Control Register 2 */
volatile TCTL3STR _TCTL3;                                  /* Timer Control Register 3 */
volatile TCTL4STR _TCTL4;                                  /* Timer Control Register 4 */
volatile TFLG1STR _TFLG1;                                  /* Main Timer Interrupt Flag 1 */
volatile TFLG2STR _TFLG2;                                  /* Main Timer Interrupt Flag 2 */
volatile TIESTR _TIE;                                      /* Timer Interrupt Enable Register */
volatile TIOSSTR _TIOS;                                    /* Timer Input Capture/Output Compare Select */
volatile TSCR1STR _TSCR1;                                  /* Timer System Control Register1 */
volatile TSCR2STR _TSCR2;                                  /* Timer System Control Register 2 */
volatile TTOVSTR _TTOV;                                    /* Timer Toggle On Overflow Register */
volatile VREGCTRLSTR _VREGCTRL;                            /* VREG_3V3 - Control Register */
volatile WOMMSTR _WOMM;                                    /* Port M Wired-Or Mode Register */
volatile WOMSSTR _WOMS;                                    /* Port S Wired-Or Mode Register */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile ATDCTL23STR _ATDCTL23;                            /* ATD Control Register 23 */
volatile ATDCTL45STR _ATDCTL45;                            /* ATD Control Register 45 */
volatile ATDDIENSTR _ATDDIEN;                              /* ATD Input Enable Register */
volatile ATDDR0STR _ATDDR0;                                /* ATD Conversion Result Register 0 */
volatile ATDDR1STR _ATDDR1;                                /* ATD Conversion Result Register 1 */
volatile ATDDR10STR _ATDDR10;                              /* ATD Conversion Result Register 10 */
volatile ATDDR11STR _ATDDR11;                              /* ATD Conversion Result Register 11 */
volatile ATDDR12STR _ATDDR12;                              /* ATD Conversion Result Register 12 */
volatile ATDDR13STR _ATDDR13;                              /* ATD Conversion Result Register 13 */
volatile ATDDR14STR _ATDDR14;                              /* ATD Conversion Result Register 14 */
volatile ATDDR15STR _ATDDR15;                              /* ATD Conversion Result Register 15 */
volatile ATDDR2STR _ATDDR2;                                /* ATD Conversion Result Register 2 */
volatile ATDDR3STR _ATDDR3;                                /* ATD Conversion Result Register 3 */
volatile ATDDR4STR _ATDDR4;                                /* ATD Conversion Result Register 4 */
volatile ATDDR5STR _ATDDR5;                                /* ATD Conversion Result Register 5 */
volatile ATDDR6STR _ATDDR6;                                /* ATD Conversion Result Register 6 */
volatile ATDDR7STR _ATDDR7;                                /* ATD Conversion Result Register 7 */
volatile ATDDR8STR _ATDDR8;                                /* ATD Conversion Result Register 8 */
volatile ATDDR9STR _ATDDR9;                                /* ATD Conversion Result Register 9 */
volatile CAN0RXTSRSTR _CAN0RXTSR;                          /* MSCAN 0 Receive Time Stamp Register */
volatile CAN0TXTSRSTR _CAN0TXTSR;                          /* MSCAN 0 Transmit Time Stamp Register */
volatile CAN1RXTSRSTR _CAN1RXTSR;                          /* MSCAN 1 Receive Time Stamp Register */
volatile CAN1TXTSRSTR _CAN1TXTSR;                          /* MSCAN 1 Transmit Time Stamp Register */
volatile DBGCASTR _DBGCA;                                  /* Debug Comparator A Register */
volatile DBGCBSTR _DBGCB;                                  /* Debug Comparator B Register */
volatile DBGCCSTR _DBGCC;                                  /* Debug Comparator C Register */
volatile DBGTBSTR _DBGTB;                                  /* Debug Trace Buffer Register */
volatile DDRABSTR _DDRAB;                                  /* Port AB Data Direction Register */
volatile ITG0ACCSTR _ITG0ACC;                              /* SSD 0 Integration Accumulator register */
volatile ITG1ACCSTR _ITG1ACC;                              /* SSD 1 Integration Accumulator register */
volatile ITG2ACCSTR _ITG2ACC;                              /* SSD 2 Integration Accumulator register */
volatile ITG3ACCSTR _ITG3ACC;                              /* SSD 3 Integration Accumulator register */
volatile MCDC0STR _MCDC0;                                  /* Motor Controller Duty Cycle Register 0 */
volatile MCDC1STR _MCDC1;                                  /* Motor Controller Duty Cycle Register 1 */
volatile MCDC2STR _MCDC2;                                  /* Motor Controller Duty Cycle Register 2 */
volatile MCDC3STR _MCDC3;                                  /* Motor Controller Duty Cycle Register 3 */
volatile MCDC4STR _MCDC4;                                  /* Motor Controller Duty Cycle Register 4 */
volatile MCDC5STR _MCDC5;                                  /* Motor Controller Duty Cycle Register 5 */
volatile MCDC6STR _MCDC6;                                  /* Motor Controller Duty Cycle Register 6 */
volatile MCDC7STR _MCDC7;                                  /* Motor Controller Duty Cycle Register 7 */
volatile MCPERSTR _MCPER;                                  /* Motor Controller Period Register, with DITH = 0 */
volatile MDC0CNTSTR _MDC0CNT;                              /* SSD 0 Modulus Down-Counter Count register */
volatile MDC1CNTSTR _MDC1CNT;                              /* SSD 1 Modulus Down-Counter Count register */
volatile MDC2CNTSTR _MDC2CNT;                              /* SSD 2 Modulus Down-Counter Count register */
volatile MDC3CNTSTR _MDC3CNT;                              /* SSD 3 Modulus Down-Counter Count register */
volatile PACNTSTR _PACNT;                                  /* Pulse Accumulators Count Register */
volatile PARTIDSTR _PARTID;                                /* Part ID Register */
volatile PORTABSTR _PORTAB;                                /* Port AB Register */
volatile PORTADSTR _PORTAD;                                /* Port AD0 Data */
volatile PWMCNT01STR _PWMCNT01;                            /* PWM Channel Counter 01 Register */
volatile PWMCNT23STR _PWMCNT23;                            /* PWM Channel Counter 23 Register */
volatile PWMCNT45STR _PWMCNT45;                            /* PWM Channel Counter 45 Register */
volatile PWMDTY01STR _PWMDTY01;                            /* PWM Channel Duty 01 Register */
volatile PWMDTY23STR _PWMDTY23;                            /* PWM Channel Duty 23 Register */
volatile PWMDTY45STR _PWMDTY45;                            /* PWM Channel Duty 45 Register */
volatile PWMPER01STR _PWMPER01;                            /* PWM Channel Period 01 Register */
volatile PWMPER23STR _PWMPER23;                            /* PWM Channel Period 23 Register */
volatile PWMPER45STR _PWMPER45;                            /* PWM Channel Period 45 Register */
volatile SCI0BDSTR _SCI0BD;                                /* SCI 0 Baud Rate Register */
volatile SCI1BDSTR _SCI1BD;                                /* SCI 1 Baud Rate Register */
volatile TC0STR _TC0;                                      /* Timer Input Capture/Output Compare Register 0 */
volatile TC1STR _TC1;                                      /* Timer Input Capture/Output Compare Register 1 */
volatile TC2STR _TC2;                                      /* Timer Input Capture/Output Compare Register 2 */
volatile TC3STR _TC3;                                      /* Timer Input Capture/Output Compare Register 3 */
volatile TC4STR _TC4;                                      /* Timer Input Capture/Output Compare Register 4 */
volatile TC5STR _TC5;                                      /* Timer Input Capture/Output Compare Register 5 */
volatile TC6STR _TC6;                                      /* Timer Input Capture/Output Compare Register 6 */
volatile TC7STR _TC7;                                      /* Timer Input Capture/Output Compare Register 7 */
volatile TCNTSTR _TCNT;                                    /* Timer Count Register */

/* EOF */