a_spi25128_head.asm

TSM320C5000系列控制SPI25128器件的代码

***** Main header for bootload****************************
*     --------------- Notes on '5402 SPI Boot Mode ---------------
*     The SPI boot mode allows the '5402 to boot from an 8-bit serial
*     EEPROM using the SPI protocol. The mode is selected at reset via
*     the INT3 external interrupt . Proper selection of the boot mode
*     requires a high to low transition on the INT3 pin within 30 CPU
*     cycles after the '5402 is reset. 
*
*     The EEPROM must be connected to McBSP1 as follows:
*            McBSP1    EEPROM
*            ******    ******
*            BCLKX     SCK
*            BFSX      /CS
*            BDX       SI
*            BDR       SO
*            XF        /HOLD  (Optional - disables EEPROM when done)
*
*     The boot table used for programming the EEPROM is generated
*     using the 8bit serial option of the Hex conversion utility. 
*      example:
*       -bootorg SERIAL
*       -memwidth 8
*************************************************************************


         
***********************************************
*    MMR definition for c54xlp peripherals    *
*-------------  MCBSP0  ----------------------*
drr10           .set    21H     ; Data Receive Register
dxr10           .set    23H     ; Data Transmit Register
SPSA0           .set  0038H     ; Serial Port 0 Sub-bank Address Register 
SPSD0           .set  0039H     ; Serial Port 0 Sub-bank Data Register 


*-------------  MCBSP1  ----------------------*
drr11           .set    41H     ; Data Receive Register         
dxr11           .set    43H     ; Data Transmit Register
SPSA1           .set  0048H     ; Serial Port 1 Sub-bank Address Register
SPSD1           .set  0049H     ; Serial Port 1 Sub-bank Data Register

*----------- MCBSP CONTROL REGS --------------*
SPCR1_SUBADDR   .set  0000H     ; Serial Port Control Register 1 (subaddress)
SPCR2_SUBADDR   .set  0001H     ; Serial Port 1 Control Register 2 (subaddress)
RCR1_SUBADDR    .set  0002H     ; Receive Control Register 1 (subaddress)
RCR2_SUBADDR    .set  0003H     ; Receive Control Register 2 (subaddress)
XCR1_SUBADDR    .set  0004H     ; Transmit Control Register 1 (subaddress)
XCR2_SUBADDR    .set  0005H     ; Transmit Control Register 2 (subaddress)
SRGR1_SUBADDR   .set  0006H     ; Sample Rate Genarator Register 1 (subaddress)
SRGR2_SUBADDR   .set  0007H     ; Sample Rate Genarator Register 2 (subaddress)
PCR_SUBADDR     .set  000EH     ; Pin Control Register (subaddress)

*-------------CONSTANT-----------------------------------
**********************************************************



*********************************************************************
* the following subroutines are implemented:                        *
* SPI_INIT  - Initializes the McBSP for 32-bit SPI master mode.     *
* SPI_READ  - Reads a byte from the specified address.              *
* SPI_WRITE - Writes the specified byte to the specified address.   *
* SPI_RDSR  - Reads the EEPROM status register.                     *
* SPI_WRSR  - Writes the EEPROM status register.                    *
*********************************************************************

**********SPI25128 EEPROM COMMANDS*********************************** 
WREN            .set    06h      ;Set Write Enable Latch            
WRDI            .set    04h      ;Reset Write Enable Latch          
RDSR            .set    05h      ;Read Status Register              
WRSR            .set    01h      ;Write Status Register             
READ            .set    03h      ;Read Data from Memory Array       
WRITE           .set    02h      ;Write Data to Memory Array        
*********************************************************************
*********************************************************************
* SCLKDIV This constant (1 to 255) should be >= to the bit rate     *
*         divisor CLKGDV. It is used by the DELAY2B subroutine, to  *
*         generate a 2-bit delay for settling time during McBSP     *
*         initialization.                                           *
*********************************************************************
SCLKDIV         .set    250     ;Running very slow for a 1.8V EEPROM
*********************************************************************
*********************************************************************
*******McBSP1  Sub-bank addressed registers****************************           
*********************************************************************
SPCR1_sub       .set    00h     ;Serial Port Control Register 1.
SPCR2_sub       .set    01h     ;Serial Port Control Register 2.
RCR1_sub        .set    02h     ;Recieve Control Register 1.
RCR2_sub        .set    03h     ;Recieve Control Register 2.
XCR1_sub        .set    04h     ;Transmit Control Register 1.
XCR2_sub        .set    05h     ;Transmit Control Register 2.
SRGR1_sub       .set    06h     ;Sample Rate Generator Register 1.
SRGR2_sub       .set    07h     ;Sample Rate Generator Register 2.
PCR_sub         .set    0Eh     ;Pin Control Register.
*********************************************************************