counter10.vhd

来自「这个是数字电子时钟」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(3 downto 0);
c:out std_logic);
end counter10;
architecture Behavioral of counter10 is
signal count : std_logic_vector(3 downto 0);
begin
dout <= count;
process(clk,reset,din)
begin
if reset='0'then
count <= din ;
c<='0';
elsif rising_edge(clk) then
if count = "1001" then
count <= "0000";
c<='1';
else 
count <= count+1;
c<='0';
end if;
end if;
end process;
end Behavioral;