clock.tan.qmsg

这个是数字电子时钟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register counter24:u4\|count\[0\] counter24:u4\|count\[5\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"counter24:u4\|count\[0\]\" and destination register \"counter24:u4\|count\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.669 ns + Longest register register " "Info: + Longest register to register delay is 2.669 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u4\|count\[0\] 1 REG LC_X16_Y2_N4 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y2_N4; Fanout = 13; REG Node = 'counter24:u4\|count\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter24:u4|count[0] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.442 ns) 1.365 ns counter24:u4\|Equal0~36 2 COMB LC_X17_Y2_N4 2 " "Info: 2: + IC(0.923 ns) + CELL(0.442 ns) = 1.365 ns; Loc. = LC_X17_Y2_N4; Fanout = 2; COMB Node = 'counter24:u4\|Equal0~36'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.365 ns" { counter24:u4|count[0] counter24:u4|Equal0~36 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.607 ns) 2.669 ns counter24:u4\|count\[5\] 3 REG LC_X16_Y2_N8 5 " "Info: 3: + IC(0.697 ns) + CELL(0.607 ns) = 2.669 ns; Loc. = LC_X16_Y2_N8; Fanout = 5; REG Node = 'counter24:u4\|count\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.304 ns" { counter24:u4|Equal0~36 counter24:u4|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.049 ns ( 39.30 % ) " "Info: Total cell delay = 1.049 ns ( 39.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.620 ns ( 60.70 % ) " "Info: Total interconnect delay = 1.620 ns ( 60.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { counter24:u4|count[0] counter24:u4|Equal0~36 counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { counter24:u4|count[0] counter24:u4|Equal0~36 counter24:u4|count[5] } { 0.000ns 0.923ns 0.697ns } { 0.000ns 0.442ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 21.888 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 21.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/dzsz/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter10:u0\|c 2 REG LC_X6_Y5_N8 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter10:u0|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.281 ns) + CELL(0.935 ns) 8.170 ns counter6:u1\|c 3 REG LC_X8_Y6_N4 5 " "Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.216 ns" { counter10:u0|c counter6:u1|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.935 ns) 12.604 ns counter10:u2\|c 4 REG LC_X26_Y6_N2 4 " "Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.434 ns" { counter6:u1|c counter10:u2|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.935 ns) 17.245 ns counter6:u3\|c 5 REG LC_X25_Y6_N9 6 " "Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.641 ns" { counter10:u2|c counter6:u3|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.932 ns) + CELL(0.711 ns) 21.888 ns counter24:u4\|count\[5\] 6 REG LC_X16_Y2_N8 5 " "Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N8; Fanout = 5; REG Node = 'counter24:u4\|count\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.643 ns" { counter6:u3|c counter24:u4|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 27.05 % ) " "Info: Total cell delay = 5.920 ns ( 27.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.968 ns ( 72.95 % ) " "Info: Total interconnect delay = 15.968 ns ( 72.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.888 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 21.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/dzsz/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter10:u0\|c 2 REG LC_X6_Y5_N8 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter10:u0|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.281 ns) + CELL(0.935 ns) 8.170 ns counter6:u1\|c 3 REG LC_X8_Y6_N4 5 " "Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.216 ns" { counter10:u0|c counter6:u1|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.935 ns) 12.604 ns counter10:u2\|c 4 REG LC_X26_Y6_N2 4 " "Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.434 ns" { counter6:u1|c counter10:u2|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.935 ns) 17.245 ns counter6:u3\|c 5 REG LC_X25_Y6_N9 6 " "Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.641 ns" { counter10:u2|c counter6:u3|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.932 ns) + CELL(0.711 ns) 21.888 ns counter24:u4\|count\[0\] 6 REG LC_X16_Y2_N4 13 " "Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N4; Fanout = 13; REG Node = 'counter24:u4\|count\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.643 ns" { counter6:u3|c counter24:u4|count[0] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 27.05 % ) " "Info: Total cell delay = 5.920 ns ( 27.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.968 ns ( 72.95 % ) " "Info: Total interconnect delay = 15.968 ns ( 72.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.669 ns" { counter24:u4|count[0] counter24:u4|Equal0~36 counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.669 ns" { counter24:u4|count[0] counter24:u4|Equal0~36 counter24:u4|count[5] } { 0.000ns 0.923ns 0.697ns } { 0.000ns 0.442ns 0.607ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[5] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[0] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter24:u4|count[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { counter24:u4|count[5] } {  } {  } } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk hourh\[5\] counter24:u4\|count\[1\] 28.711 ns register " "Info: tco from clock \"clk\" to destination pin \"hourh\[5\]\" through register \"counter24:u4\|count\[1\]\" is 28.711 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.888 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 21.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/dzsz/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter10:u0\|c 2 REG LC_X6_Y5_N8 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter10:u0|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.281 ns) + CELL(0.935 ns) 8.170 ns counter6:u1\|c 3 REG LC_X8_Y6_N4 5 " "Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.216 ns" { counter10:u0|c counter6:u1|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.935 ns) 12.604 ns counter10:u2\|c 4 REG LC_X26_Y6_N2 4 " "Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.434 ns" { counter6:u1|c counter10:u2|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "D:/dzsz/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.935 ns) 17.245 ns counter6:u3\|c 5 REG LC_X25_Y6_N9 6 " "Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3\|c'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.641 ns" { counter10:u2|c counter6:u3|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "D:/dzsz/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.932 ns) + CELL(0.711 ns) 21.888 ns counter24:u4\|count\[1\] 6 REG LC_X16_Y2_N5 13 " "Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N5; Fanout = 13; REG Node = 'counter24:u4\|count\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.643 ns" { counter6:u3|c counter24:u4|count[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 27.05 % ) " "Info: Total cell delay = 5.920 ns ( 27.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.968 ns ( 72.95 % ) " "Info: Total interconnect delay = 15.968 ns ( 72.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[1] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.599 ns + Longest register pin " "Info: + Longest register to pin delay is 6.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u4\|count\[1\] 1 REG LC_X16_Y2_N5 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y2_N5; Fanout = 13; REG Node = 'counter24:u4\|count\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter24:u4|count[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "D:/dzsz/counter24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.312 ns) + CELL(0.590 ns) 1.902 ns decoder:u9\|Mux1~21 2 COMB LC_X17_Y2_N1 1 " "Info: 2: + IC(1.312 ns) + CELL(0.590 ns) = 1.902 ns; Loc. = LC_X17_Y2_N1; Fanout = 1; COMB Node = 'decoder:u9\|Mux1~21'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.902 ns" { counter24:u4|count[1] decoder:u9|Mux1~21 } "NODE_NAME" } } { "decoder.vhd" "" { Text "D:/dzsz/decoder.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.589 ns) + CELL(2.108 ns) 6.599 ns hourh\[5\] 3 PIN PIN_121 0 " "Info: 3: + IC(2.589 ns) + CELL(2.108 ns) = 6.599 ns; Loc. = PIN_121; Fanout = 0; PIN Node = 'hourh\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.697 ns" { decoder:u9|Mux1~21 hourh[5] } "NODE_NAME" } } { "clock.vhd" "" { Text "D:/dzsz/clock.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 40.88 % ) " "Info: Total cell delay = 2.698 ns ( 40.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.901 ns ( 59.12 % ) " "Info: Total interconnect delay = 3.901 ns ( 59.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.599 ns" { counter24:u4|count[1] decoder:u9|Mux1~21 hourh[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.599 ns" { counter24:u4|count[1] decoder:u9|Mux1~21 hourh[5] } { 0.000ns 1.312ns 2.589ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.888 ns" { clk counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.888 ns" { clk clk~out0 counter10:u0|c counter6:u1|c counter10:u2|c counter6:u3|c counter24:u4|count[1] } { 0.000ns 0.000ns 0.550ns 4.281ns 3.499ns 3.706ns 3.932ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.599 ns" { counter24:u4|count[1] decoder:u9|Mux1~21 hourh[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.599 ns" { counter24:u4|count[1] decoder:u9|Mux1~21 hourh[5] } { 0.000ns 1.312ns 2.589ns } { 0.000ns 0.590ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 05 09:21:28 2008 " "Info: Processing ended: Thu Jun 05 09:21:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}