clock.sim.rpt

这个是数字电子时钟

; |clock|counter24:u4|count[0]                                                       ; |clock|counter24:u4|count[0]                                                            ; out              ;
; |clock|counter24:u4|count~0                                                        ; |clock|counter24:u4|count~0                                                             ; out              ;
; |clock|counter24:u4|count~1                                                        ; |clock|counter24:u4|count~1                                                             ; out              ;
; |clock|counter24:u4|count~2                                                        ; |clock|counter24:u4|count~2                                                             ; out              ;
; |clock|counter24:u4|count~3                                                        ; |clock|counter24:u4|count~3                                                             ; out              ;
; |clock|counter24:u4|count~4                                                        ; |clock|counter24:u4|count~4                                                             ; out              ;
; |clock|counter24:u4|count~5                                                        ; |clock|counter24:u4|count~5                                                             ; out              ;
; |clock|counter24:u4|count~6                                                        ; |clock|counter24:u4|count~6                                                             ; out              ;
; |clock|counter24:u4|count~7                                                        ; |clock|counter24:u4|count~7                                                             ; out              ;
; |clock|counter24:u4|count~8                                                        ; |clock|counter24:u4|count~8                                                             ; out              ;
; |clock|counter24:u4|count~9                                                        ; |clock|counter24:u4|count~9                                                             ; out              ;
; |clock|counter24:u4|count~10                                                       ; |clock|counter24:u4|count~10                                                            ; out              ;
; |clock|counter24:u4|count~11                                                       ; |clock|counter24:u4|count~11                                                            ; out              ;
; |clock|counter24:u4|count[1]                                                       ; |clock|counter24:u4|count[1]                                                            ; out              ;
; |clock|counter24:u4|count[2]                                                       ; |clock|counter24:u4|count[2]                                                            ; out              ;
; |clock|counter24:u4|count[3]                                                       ; |clock|counter24:u4|count[3]                                                            ; out              ;
; |clock|counter24:u4|count[4]                                                       ; |clock|counter24:u4|count[4]                                                            ; out              ;
; |clock|counter24:u4|count[5]                                                       ; |clock|counter24:u4|count[5]                                                            ; out              ;
; |clock|counter6:u3|count~0                                                         ; |clock|counter6:u3|count~0                                                              ; out              ;
; |clock|counter6:u3|count~1                                                         ; |clock|counter6:u3|count~1                                                              ; out              ;
; |clock|counter6:u3|count~2                                                         ; |clock|counter6:u3|count~2                                                              ; out              ;
; |clock|counter6:u3|count[0]                                                        ; |clock|counter6:u3|count[0]                                                             ; out              ;
; |clock|counter10:u2|count~0                                                        ; |clock|counter10:u2|count~0                                                             ; out              ;
; |clock|counter10:u2|count~1                                                        ; |clock|counter10:u2|count~1                                                             ; out              ;
; |clock|counter10:u2|count~2                                                        ; |clock|counter10:u2|count~2                                                             ; out              ;
; |clock|counter10:u2|count~3                                                        ; |clock|counter10:u2|count~3                                                             ; out              ;
; |clock|counter10:u2|count[0]                                                       ; |clock|counter10:u2|count[0]                                                            ; out              ;
; |clock|counter10:u2|count[1]                                                       ; |clock|counter10:u2|count[1]                                                            ; out              ;
; |clock|counter10:u2|count[2]                                                       ; |clock|counter10:u2|count[2]                                                            ; out              ;
; |clock|counter10:u2|count[3]                                                       ; |clock|counter10:u2|count[3]                                                            ; out              ;
; |clock|counter6:u1|count~0                                                         ; |clock|counter6:u1|count~0                                                              ; out              ;
; |clock|counter6:u1|count~1                                                         ; |clock|counter6:u1|count~1                                                              ; out              ;
; |clock|counter6:u1|count~2                                                         ; |clock|counter6:u1|count~2                                                              ; out              ;
; |clock|counter6:u1|count[0]                                                        ; |clock|counter6:u1|count[0]                                                             ; out              ;
; |clock|counter10:u0|count~0                                                        ; |clock|counter10:u0|count~0                                                             ; out              ;
; |clock|counter10:u0|count~1                                                        ; |clock|counter10:u0|count~1                                                             ; out              ;
; |clock|counter10:u0|count~2                                                        ; |clock|counter10:u0|count~2                                                             ; out              ;
; |clock|counter10:u0|count~3                                                        ; |clock|counter10:u0|count~3                                                             ; out              ;
; |clock|counter10:u0|count[0]                                                       ; |clock|counter10:u0|count[0]                                                            ; out              ;
; |clock|counter10:u0|count[1]                                                       ; |clock|counter10:u0|count[1]                                                            ; out              ;
; |clock|counter10:u0|count[2]                                                       ; |clock|counter10:u0|count[2]                                                            ; out              ;
; |clock|counter10:u0|count[3]                                                       ; |clock|counter10:u0|count[3]                                                            ; out              ;
; |clock|counter24:u4|Equal0~5                                                       ; |clock|counter24:u4|Equal0~5                                                            ; out0             ;
; |clock|counter24:u4|Equal1~7                                                       ; |clock|counter24:u4|Equal1~7                                                            ; out0             ;
; |clock|counter10:u2|Equal0~5                                                       ; |clock|counter10:u2|Equal0~5                                                            ; out0             ;
; |clock|counter10:u0|Equal0~5                                                       ; |clock|counter10:u0|Equal0~5                                                            ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|result_node[0]                                ; |clock|counter10:u0|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|result_node[1]                                ; |clock|counter10:u0|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|result_node[2]                                ; |clock|counter10:u0|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|result_node[3]                                ; |clock|counter10:u0|lpm_add_sub:Add0|result_node[3]                                     ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~0                             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~3                             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]               ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~7                             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~7                                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~8                             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~8                                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~9                             ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~9                                  ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~10                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~10                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~11                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~11                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~12                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~12                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~13                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~13                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~14                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~14                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~15                            ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|_~15                                 ; out0             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |clock|counter10:u0|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
; |clock|counter6:u1|lpm_add_sub:Add0|result_node[0]                                 ; |clock|counter6:u1|lpm_add_sub:Add0|result_node[0]                                      ; out0             ;
; |clock|counter6:u1|lpm_add_sub:Add0|result_node[1]                                 ; |clock|counter6:u1|lpm_add_sub:Add0|result_node[1]                                      ; out0             ;
; |clock|counter6:u1|lpm_add_sub:Add0|result_node[2]                                 ; |clock|counter6:u1|lpm_add_sub:Add0|result_node[2]                                      ; out0             ;
; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0              ; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                   ; out0             ;
; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                ; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                     ; out0             ;
; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|_~0                              ; |clock|counter6:u1|lpm_add_sub:Add0|addcore:adder|_~0                                   ; out0             ;