clock.tan.rpt

这个是数字电子时钟

; N/A   ; None         ; 17.197 ns  ; counter10:u2|count[3] ; minutel[4] ; clk        ;
; N/A   ; None         ; 17.181 ns  ; counter10:u2|count[1] ; minutel[5] ; clk        ;
; N/A   ; None         ; 17.180 ns  ; counter10:u2|count[1] ; minutel[6] ; clk        ;
; N/A   ; None         ; 17.166 ns  ; counter10:u2|count[1] ; minutel[3] ; clk        ;
; N/A   ; None         ; 17.159 ns  ; counter10:u2|count[1] ; minutel[2] ; clk        ;
; N/A   ; None         ; 17.047 ns  ; counter10:u2|count[3] ; minutel[5] ; clk        ;
; N/A   ; None         ; 17.034 ns  ; counter10:u2|count[3] ; minutel[6] ; clk        ;
; N/A   ; None         ; 17.026 ns  ; counter10:u2|count[3] ; minutel[3] ; clk        ;
; N/A   ; None         ; 17.016 ns  ; counter10:u2|count[3] ; minutel[2] ; clk        ;
; N/A   ; None         ; 14.333 ns  ; counter6:u1|count[0]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 14.314 ns  ; counter6:u1|count[0]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 14.220 ns  ; counter6:u1|count[0]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 14.002 ns  ; counter6:u1|count[0]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 14.002 ns  ; counter6:u1|count[0]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 13.917 ns  ; counter6:u1|count[0]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 13.911 ns  ; counter6:u1|count[0]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 13.374 ns  ; counter6:u1|count[2]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 13.361 ns  ; counter6:u1|count[2]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 13.262 ns  ; counter6:u1|count[2]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 13.207 ns  ; counter6:u1|count[1]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 13.201 ns  ; counter6:u1|count[1]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 13.103 ns  ; counter6:u1|count[1]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 13.049 ns  ; counter6:u1|count[2]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 13.044 ns  ; counter6:u1|count[2]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 12.958 ns  ; counter6:u1|count[2]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 12.952 ns  ; counter6:u1|count[2]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 12.895 ns  ; counter6:u1|count[1]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 12.880 ns  ; counter6:u1|count[1]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 12.785 ns  ; counter6:u1|count[1]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 12.779 ns  ; counter6:u1|count[1]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 9.465 ns   ; counter10:u0|count[0] ; secondl[1] ; clk        ;
; N/A   ; None         ; 9.225 ns   ; counter10:u0|count[3] ; secondl[1] ; clk        ;
; N/A   ; None         ; 9.153 ns   ; counter10:u0|count[0] ; secondl[3] ; clk        ;
; N/A   ; None         ; 9.127 ns   ; counter10:u0|count[0] ; secondl[2] ; clk        ;
; N/A   ; None         ; 9.094 ns   ; counter10:u0|count[0] ; secondl[0] ; clk        ;
; N/A   ; None         ; 9.041 ns   ; counter10:u0|count[3] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.930 ns   ; counter10:u0|count[3] ; secondl[3] ; clk        ;
; N/A   ; None         ; 8.898 ns   ; counter10:u0|count[3] ; secondl[2] ; clk        ;
; N/A   ; None         ; 8.861 ns   ; counter10:u0|count[1] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.856 ns   ; counter10:u0|count[3] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.686 ns   ; counter10:u0|count[0] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.664 ns   ; counter10:u0|count[0] ; secondl[5] ; clk        ;
; N/A   ; None         ; 8.555 ns   ; counter10:u0|count[2] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.458 ns   ; counter10:u0|count[1] ; secondl[1] ; clk        ;
; N/A   ; None         ; 8.447 ns   ; counter10:u0|count[3] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.429 ns   ; counter10:u0|count[3] ; secondl[5] ; clk        ;
; N/A   ; None         ; 8.300 ns   ; counter10:u0|count[2] ; secondl[1] ; clk        ;
; N/A   ; None         ; 8.157 ns   ; counter10:u0|count[1] ; secondl[3] ; clk        ;
; N/A   ; None         ; 8.127 ns   ; counter10:u0|count[1] ; secondl[2] ; clk        ;
; N/A   ; None         ; 8.088 ns   ; counter10:u0|count[1] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.026 ns   ; counter10:u0|count[0] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.018 ns   ; counter10:u0|count[2] ; secondl[3] ; clk        ;
; N/A   ; None         ; 7.987 ns   ; counter10:u0|count[2] ; secondl[2] ; clk        ;
; N/A   ; None         ; 7.930 ns   ; counter10:u0|count[2] ; secondl[0] ; clk        ;
; N/A   ; None         ; 7.680 ns   ; counter10:u0|count[1] ; secondl[4] ; clk        ;
; N/A   ; None         ; 7.658 ns   ; counter10:u0|count[1] ; secondl[5] ; clk        ;
; N/A   ; None         ; 7.522 ns   ; counter10:u0|count[2] ; secondl[4] ; clk        ;
; N/A   ; None         ; 7.505 ns   ; counter10:u0|count[2] ; secondl[5] ; clk        ;
+-------+--------------+------------+-----------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jun 05 09:21:28 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter6:u3|c" as buffer
    Info: Detected ripple clock "counter10:u2|c" as buffer
    Info: Detected ripple clock "counter6:u1|c" as buffer
    Info: Detected ripple clock "counter10:u0|c" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "counter24:u4|count[0]" and destination register "counter24:u4|count[5]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.669 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y2_N4; Fanout = 13; REG Node = 'counter24:u4|count[0]'
            Info: 2: + IC(0.923 ns) + CELL(0.442 ns) = 1.365 ns; Loc. = LC_X17_Y2_N4; Fanout = 2; COMB Node = 'counter24:u4|Equal0~36'
            Info: 3: + IC(0.697 ns) + CELL(0.607 ns) = 2.669 ns; Loc. = LC_X16_Y2_N8; Fanout = 5; REG Node = 'counter24:u4|count[5]'
            Info: Total cell delay = 1.049 ns ( 39.30 % )
            Info: Total interconnect delay = 1.620 ns ( 60.70 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 21.888 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0|c'
                Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1|c'
                Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2|c'
                Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3|c'
                Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N8; Fanout = 5; REG Node = 'counter24:u4|count[5]'
                Info: Total cell delay = 5.920 ns ( 27.05 % )
                Info: Total interconnect delay = 15.968 ns ( 72.95 % )
            Info: - Longest clock path from clock "clk" to source register is 21.888 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0|c'
                Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1|c'
                Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2|c'
                Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3|c'
                Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N4; Fanout = 13; REG Node = 'counter24:u4|count[0]'
                Info: Total cell delay = 5.920 ns ( 27.05 % )
                Info: Total interconnect delay = 15.968 ns ( 72.95 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "hourh[5]" through register "counter24:u4|count[1]" is 28.711 ns
    Info: + Longest clock path from clock "clk" to source register is 21.888 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X6_Y5_N8; Fanout = 4; REG Node = 'counter10:u0|c'
        Info: 3: + IC(4.281 ns) + CELL(0.935 ns) = 8.170 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'counter6:u1|c'
        Info: 4: + IC(3.499 ns) + CELL(0.935 ns) = 12.604 ns; Loc. = LC_X26_Y6_N2; Fanout = 4; REG Node = 'counter10:u2|c'
        Info: 5: + IC(3.706 ns) + CELL(0.935 ns) = 17.245 ns; Loc. = LC_X25_Y6_N9; Fanout = 6; REG Node = 'counter6:u3|c'
        Info: 6: + IC(3.932 ns) + CELL(0.711 ns) = 21.888 ns; Loc. = LC_X16_Y2_N5; Fanout = 13; REG Node = 'counter24:u4|count[1]'
        Info: Total cell delay = 5.920 ns ( 27.05 % )
        Info: Total interconnect delay = 15.968 ns ( 72.95 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 6.599 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y2_N5; Fanout = 13; REG Node = 'counter24:u4|count[1]'
        Info: 2: + IC(1.312 ns) + CELL(0.590 ns) = 1.902 ns; Loc. = LC_X17_Y2_N1; Fanout = 1; COMB Node = 'decoder:u9|Mux1~21'
        Info: 3: + IC(2.589 ns) + CELL(2.108 ns) = 6.599 ns; Loc. = PIN_121; Fanout = 0; PIN Node = 'hourh[5]'
        Info: Total cell delay = 2.698 ns ( 40.88 % )
        Info: Total interconnect delay = 3.901 ns ( 59.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jun 05 09:21:28 2008
    Info: Elapsed time: 00:00:01