clock.tan.rpt

这个是数字电子时钟

Timing Analyzer report for clock
Thu Jun 05 09:21:28 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                      ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                  ; To                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 28.711 ns                                      ; counter24:u4|count[1] ; hourh[5]              ; clk        ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[5] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                       ;                       ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------+-----------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                 ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                  ; To                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[5] ; clk        ; clk      ; None                        ; None                      ; 2.669 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[2] ; counter24:u4|count[5] ; clk        ; clk      ; None                        ; None                      ; 2.651 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 2.406 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 2.402 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[4] ; clk        ; clk      ; None                        ; None                      ; 2.385 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[1] ; counter24:u4|count[5] ; clk        ; clk      ; None                        ; None                      ; 2.380 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[3] ; counter24:u4|count[5] ; clk        ; clk      ; None                        ; None                      ; 2.368 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[2] ; counter24:u4|count[4] ; clk        ; clk      ; None                        ; None                      ; 2.367 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[1] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 2.351 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[5] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 2.179 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[2] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 2.175 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[5] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 2.175 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[2] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 2.171 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[0] ; counter10:u2|count[1] ; clk        ; clk      ; None                        ; None                      ; 2.182 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[0] ; counter24:u4|count[2] ; clk        ; clk      ; None                        ; None                      ; 2.122 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[1] ; counter24:u4|count[4] ; clk        ; clk      ; None                        ; None                      ; 2.096 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[3] ; counter24:u4|count[4] ; clk        ; clk      ; None                        ; None                      ; 2.084 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u0|count[0] ; counter10:u0|c        ; clk        ; clk      ; None                        ; None                      ; 2.077 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[4] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 1.988 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[4] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 1.984 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[4] ; counter24:u4|count[5] ; clk        ; clk      ; None                        ; None                      ; 1.943 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[1] ; counter24:u4|count[2] ; clk        ; clk      ; None                        ; None                      ; 1.943 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[1] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 1.943 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[1] ; counter10:u2|c        ; clk        ; clk      ; None                        ; None                      ; 1.928 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[1] ; counter10:u2|count[3] ; clk        ; clk      ; None                        ; None                      ; 1.927 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[3] ; counter24:u4|count[1] ; clk        ; clk      ; None                        ; None                      ; 1.912 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[3] ; counter24:u4|count[3] ; clk        ; clk      ; None                        ; None                      ; 1.908 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[5] ; counter24:u4|count[2] ; clk        ; clk      ; None                        ; None                      ; 1.895 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter24:u4|count[2] ; counter24:u4|count[2] ; clk        ; clk      ; None                        ; None                      ; 1.891 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[0] ; counter10:u2|count[3] ; clk        ; clk      ; None                        ; None                      ; 1.889 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u3|count[0]  ; counter6:u3|c         ; clk        ; clk      ; None                        ; None                      ; 1.824 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u3|count[0]  ; counter6:u3|count[2]  ; clk        ; clk      ; None                        ; None                      ; 1.818 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u3|count[0]  ; counter6:u3|count[1]  ; clk        ; clk      ; None                        ; None                      ; 1.816 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u1|count[0]  ; counter6:u1|count[1]  ; clk        ; clk      ; None                        ; None                      ; 1.794 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u1|count[0]  ; counter6:u1|c         ; clk        ; clk      ; None                        ; None                      ; 1.792 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter6:u1|count[0]  ; counter6:u1|count[2]  ; clk        ; clk      ; None                        ; None                      ; 1.784 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[0] ; counter10:u2|c        ; clk        ; clk      ; None                        ; None                      ; 1.799 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[2] ; counter10:u2|c        ; clk        ; clk      ; None                        ; None                      ; 1.791 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[2] ; counter10:u2|count[3] ; clk        ; clk      ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; counter10:u2|count[2] ; counter10:u2|count[1] ; clk        ; clk      ; None                        ; None                      ; 1.782 ns                ;