tb_cla16.v

来自「carry lookahead adder verilog program」· Verilog 代码 · 共 47 行

`timescale 1ns/100ps

module tb_cla16;
    parameter samples = 100;
    parameter n = 16;        
    reg [n-1:0]    a,b;
    reg Cin;
    wire Cout;
    wire [n-1:0]    Sum;
    integer i;
    reg [3*n+1:0] temp;
cla16 UUT(.a(a),.b(b),.Cin(Cin),.Cout(Cout),.s(Sum));

  function [1+n+n+n+1-1:0] gen_rand_data;
     input integer  i;
     reg Cin;
     reg [n-1:0] a;
     reg [n-1:0] b;
     reg [n-1:0] Sum;
     reg Cout;
     begin
         a = {$random};
         b = {$random};
         Cin= {$random};
         {Cout, Sum} = a + b + {{n-1{1'b0}}, Cin};     
 gen_rand_data = {Cin,a[n-1:0],b[n-1:0],Cout,Sum[n-1:0]};
     end
  endfunction


   initial   begin
#10 
    for(i=1; i<=samples; i=i+1) 
    begin
           temp=gen_rand_data(i);
           {Cin,a[n-1:0],b[n-1:0]}=temp[3*n+1:n+1];
             #10  if({Cout,Sum[n-1:0]}==temp[n:0]) 
	            $display("--result correct--");
	          else
            $display($realtime,,"bad result: Cin=1'b%b,a=n-1'b%b,b=n-1'b%b,Cout=1'b%b, Sum=n-1'b%b",Cin,a,b,Cout,Sum);
           	end
			#10 a={16'b1};b={16{1'b1}};
            #10
            $stop;
    end
endmodule