cla_dc.tcl

a demo script of "carry lookahead adder" for synopsys design compiler

####### Set Directary ######################
set LIB typical 
set HOME "/home/xhwc"
set SYNDIR $HOME 
set SRCDIR $HOME/src 
set SCRDIR $HOME/script 
set RPTDIR $HOME/rpt
set SYNDB   $HOME/db
set SYNOPSYS_DC "/usr/synopsys/dc"
set SYNOPSYS_TSMC "/usr/synopsys/lib/tsmc/aci/sc"

set search_path ". $SYNOPSYS_DC/libraries/syn\  
                   $SYNOPSYS_TSMC"
                  #$SYNOPSYS_DC/dw/sim_ver
set target_library "$SYNOPSYS_TSMC/synopsys/slow.db\
                    $SYNOPSYS_TSMC/synopsys/typical.db"  
set symbol_library "$SYNOPSYS_TSMC/symbols/synopsys/tsmc18.sdb"
set link_library "* $target_library\
                    $SYNOPSYS_TSMC/symbols/synopsys/tsmc18.sdb"
                   #$SYNOPSYS_DC/libraries/syn/dw_foundation.sldb 
          
set verilogout_no_tri true
                   
############ 设定门控时钟常用变量 ##################                    
#set hdlin_enable_rtldrc_info true
#set power_preserve_rtl_hier_names true
########### 设定门控时钟类型及相关参数 #############
#set_clock_gating_style -sequential_cell latch -setup 0.2 -hold 0.1 -control_point before -control_signal scan_enable 
       
###################################################              
#read_file -format verilog {/home/xhwc/src/cla.v /home/xhwc/src/cla_top.v /home/xhwc/src/claadder.v /home/xhwc/src/lcla.v /home/xhwc/src/pg.v}
#analyze -format verilog {/home/xhwc/src/cla_top.v /home/xhwc/src/cla.v /home/xhwc/src/pg.v /home/xhwc/src/lcla.v /home/xhwc/src/claadder.v}
#elaborate cla_top -architecture verilog -library WORK             
#############################################
read_verilog [list $SRCDIR/cla_top.v $SRCDIR/claadder.v $SRCDIR/cla.v $SRCDIR/lcla.v $SRCDIR/pg.v]
#insert_clock_gating -module_level
#set & link top design ,remove relative constraints 
#hookup_testports -verbose 
reset_design 
link
current_design cla_top 

######### report gate_clock #################
#report_clock_gating -gating_elements -gated -ungated -hier > $RPTDIR/gate.rpt
#############################################
                                  
###################################################
set_operating_conditions -max slow -library slow -min typical -library typical  
set_wire_load_mode top
set_wire_load_model -library typical -name tsmc18_wl10 -min
set_wire_load_model -library slow -name tsmc18_wl40 -max

#ensure the postive slack,the smallest area
set_max_area 0
#recommend for reduce area
set compile_sequential_area_recovery true
set compile_new_boolean_structure true
set_structure -boolean true -boolean_effort high 

################
set_drive 10 [all_inputs]
set_fanout_load 10 [all_outputs]

######## set clock ################################
create_clock -name CLK -p 40 [get_ports clk] -waveform {0 5}
set_clock_uncertainty 0.3 CLK
set_clock_transition 0.1 CLK 
set_clock_latency -source 1 CLK
set_clock_latency 1 CLK

set_input_delay 3 -clock CLK [all_inputs]
set_output_delay 3 -clock CLK [all_outputs]
set_dont_touch_network [list clk rst_n]
set_fix_multiple_port_nets –feedthroughs
set_fix_multiple_port_nets –all –buffer_constants
#create_clock -p 40 -name Post_cg_clk4 [get_pins -hierarchical "*clk_gate*/ENCLK"]
#create_clock -p 40 -name Pre_cg_clk4 [get_pins -hierarchical "*clk_gate*/CLK"]
#set_clock_latency 0 [get_clocks {Pre_cg_clk4}]
#set_clock_latency 0.7 [get_clocks {Post_cg_clk4}]

#################################################
#derive_timing_constraints -max_delay_scale 1.00 -min_delay_scale 1.00 -period_scale 1.00

############################################################
compile -map_effort medium -incremental_mapping > $SRCDIR/complite.txt

report_timing > $RPTDIR/report_time.rpt
report_area > $RPTDIR/report_area.rpt

write -format db -hier -o $SYNDB/cla_dc.db
write -format verilog -hier -o $SYNDB/cla_gate.v
write_sdf -version 2.1 $SRCDIR/cla.sdf
write_constraints -cover_design -format sdf-v2.1 -output $SYNDB/constraints.sdf
write_script -format dctcl -output $SRCDIR/setlib.sdc
#analysis_coverage -check_type {setup hold recovery min_period clock_separation max_skew clock_gating_setup clock_gating_hold out_setup out_hold nochange }
#############################################################
########
#set flatten model  -gated_clock