system_tb.v

ddr ram controller vhdl code

1 //---------------------------------------------------------------------------- 
2 // 
3 //---------------------------------------------------------------------------- 
4 `timescale 1ns / 1ps 
5 `include "ddr_include.v" 
6  
7 module system_tb; 
8  
9 //---------------------------------------------------------------------------- 
10 // Parameter (may differ for physical synthesis) 
11 //---------------------------------------------------------------------------- 
12 parameter tck              = 10;       // clock period in ns 
13 parameter uart_baud_rate   = 115200;   // uart baud rate for simulation  
14 parameter ddr_phase_shift  = 100;      // 
15 parameter ddr_wait200_init = 1;        // 
16  
17 parameter clk_freq = 1000000000 / tck; // Frequenzy in HZ 
18  
19 //---------------------------------------------------------------------------- 
20 // 
21 //---------------------------------------------------------------------------- 
22 reg             clk; 
23 reg             reset; 
24  
25 wire [7:0]      led; 
26 reg  [2:0]      rot; 
27  
28 reg             uart_rxd; 
29 wire            uart_txd; 
30  
31 //---------------------------------------------------------------------------- 
32 // DDR connection 
33 //---------------------------------------------------------------------------- 
34 wire            ddr_clk; 
35 wire            ddr_clk_n; 
36 wire            ddr_clk_fb; 
37 wire            ddr_ras_n; 
38 wire            ddr_cas_n; 
39 wire            ddr_we_n; 
40 wire            ddr_cke; 
41 wire            ddr_cs_n; 
42 wire [  `A_RNG] ddr_a; 
43 wire [ `BA_RNG] ddr_ba; 
44 wire [ `DQ_RNG] ddr_dq; 
45 wire [`DQS_RNG] ddr_dqs; 
46 wire [ `DM_RNG] ddr_dm; 
47  
48 //---------------------------------------------------------------------------- 
49 // Memory-Tester System 
50 //---------------------------------------------------------------------------- 
51 system #( 
52         .clk_freq(         clk_freq         ), 
53         .ddr_phase_shift(  ddr_phase_shift  ), 
54         .ddr_wait200_init( ddr_wait200_init ) 
55 ) dut ( 
56         .clk(          clk   ), 
57         .reset(        reset ), 
58         // Status putput 
59         .led(          led   ), 
60         .rot(          rot   ), 
61         // LAC 
62         .uart_rxd(     uart_rxd    ), 
63         .uart_txd(     uart_txd    ), 
64         // DDR Ports 
65         .ddr_clk(      ddr_clk     ), 
66         .ddr_clk_n(    ddr_clk_n   ), 
67         .ddr_clk_fb(   ddr_clk_fb  ), 
68         .ddr_ras_n(    ddr_ras_n   ), 
69         .ddr_cas_n(    ddr_cas_n   ), 
70         .ddr_we_n(     ddr_we_n    ), 
71         .ddr_cke(      ddr_cke     ), 
72         .ddr_cs_n(     ddr_cs_n    ), 
73         .ddr_a(        ddr_a       ), 
74         .ddr_ba(       ddr_ba      ), 
75         .ddr_dq(       ddr_dq      ), 
76         .ddr_dqs(      ddr_dqs     ), 
77         .ddr_dm(       ddr_dm      ) 
78 ); 
79  
80 //---------------------------------------------------------------------------- 
81 // Micron DDR Memory 
82 //---------------------------------------------------------------------------- 
83 ddr mt46v16m16 ( 
84         .Dq(     ddr_dq    ), 
85         .Dqs(    ddr_dqs   ), 
86         .Addr(   ddr_a     ), 
87         .Ba(     ddr_ba    ), 
88         .Clk(    ddr_clk   ), 
89         .Clk_n(  ddr_clk_n ), 
90         .Cke(    ddr_cke   ), 
91         .Cs_n(   ddr_cs_n  ), 
92         .Ras_n(  ddr_ras_n ), 
93         .Cas_n(  ddr_cas_n ), 
94         .We_n(   ddr_we_n  ), 
95         .Dm(     ddr_dm    ) 
96 ); 
97  
98 assign ddr_clk_fb = ddr_clk; 
99  
100 //---------------------------------------------------------------------------- 
101 // Clock Generation 
102 //---------------------------------------------------------------------------- 
103 initial clk <= 1'b0; 
104 always #10 clk <=  ~clk; 
105  
106 //---------------------------------------------------------------------------- 
107 //  RESET Generation 
108 //---------------------------------------------------------------------------- 
109 initial begin 
110         $dumpvars; 
111         $dumpfile("system_tb.vcd"); 
112  
113         #0       reset <= 1'b1; //SPARTAN-3E STARTER KIT 
114         #80      reset <= 1'b0; 
115  
116         #150000  $finish; 
117 end 
118  
119 endmodule 
120  
121 // vim: set ts=4