system_tb.save

ddr ram controller vhdl code

1 [size] 1024 699 
2 [pos] 0 24 
3 *-26.000000 34800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
4 @28 
5 system_tb.dut.clk 
6 system_tb.dut.reset 
7 system_tb.dut.ctrl0.pulse79_gen.pulse78 
8 @200 
9 -DDR SIGNALS 
10 @28 
11 system_tb.dut.ddr_clk 
12 system_tb.dut.ddr_ras_n 
13 system_tb.dut.ddr_cas_n 
14 system_tb.dut.ddr_we_n 
15 system_tb.dut.ddr_ba[1:0] 
16 @22 
17 system_tb.dut.ddr_a[12:0] 
18 @28 
19 system_tb.dut.ddr_dqs[1:0] 
20 @22 
21 system_tb.dut.ddr_dq[15:0] 
22 @28 
23 system_tb.dut.ddr_dm[1:0] 
24 @200 
25 -FML-MEMTEST 
26 @28 
27 system_tb.dut.test0.fml_rd 
28 system_tb.dut.test0.fml_wr 
29 system_tb.dut.test0.fml_done 
30 @22 
31 system_tb.dut.test0.fml_adr[25:4] 
32 system_tb.dut.test0.fml_rdata[127:0] 
33 system_tb.dut.test0.fml_wdata[127:0] 
34 @200 
35 -DDR CONTROLLER 
36 @28 
37 system_tb.dut.ctrl0.state[1:0] 
38 system_tb.dut.ctrl0.init_done 
39 system_tb.dut.ctrl0.init_req 
40 system_tb.dut.ctrl0.ar_req 
41 system_tb.dut.ctrl0.fml_act_req 
42 system_tb.dut.ctrl0.fml_pre_req 
43 system_tb.dut.ctrl0.fml_read_req 
44 system_tb.dut.ctrl0.fml_write_req 
45 @22 
46 system_tb.dut.ctrl0.cba_fifo_din[17:0] 
47 @200 
48 -READ PATH 
49 @28 
50 system_tb.dut.ctrl0.rpath0.clk 
51 system_tb.dut.ctrl0.rpath0.sample 
52 system_tb.dut.ctrl0.rpath0.sample180 
53 @22 
54 system_tb.dut.ctrl0.rpath0.rfifo_din[31:0] 
55 system_tb.dut.ctrl0.wpath0.cba_fifo.Data_in[17:0] 
56 system_tb.dut.ctrl0.wpath0.cba_fifo.Data_out[17:0] 
57 @200 
58 -STATUS LEDS 
59 @28 
60 (0)system_tb.led[7:0] 
61 (1)system_tb.led[7:0] 
62 (2)system_tb.led[7:0] 
63 (3)system_tb.led[7:0] 
64 (4)system_tb.led[7:0] 
65 (5)system_tb.led[7:0] 
66 (6)system_tb.led[7:0] 
67 (7)system_tb.led[7:0] 
68 @22 
69 system_tb.dut.test0.fml_rdata[127:0] 
70 system_tb.dut.test0.fml_wdata[127:0] 
71 system_tb.dut.test0.r_data[127:0] 
72 system_tb.dut.test0.r_adr[25:4]