fddrrse.v

ddr ram controller vhdl code

1 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.15.48.1 2007/03/09 18:13:02 patrickp Exp $ 
2 /////////////////////////////////////////////////////////////////////////////// 
3 // Copyright (c) 1995/2004 Xilinx, Inc. 
4 // All Right Reserved. 
5 /////////////////////////////////////////////////////////////////////////////// 
6 //   ____  ____ 
7 //  /   /\/   / 
8 // /___/  \  /    Vendor : Xilinx 
9 // \   \   \/     Version : 8.1i (I.27) 
10 //  \   \         Description : Xilinx Functional Simulation Library Component 
11 //  /   /                  Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable 
12 // /___/   /\     Filename : FDDRRSE.v 
13 // \   \  /  \    Timestamp : Thu Mar 25 16:42:16 PST 2004 
14 //  \___\/\___\ 
15 // 
16 // Revision: 
17 //    03/23/04 - Initial version. 
18 //    02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. 
19 //    05/06/05 - Remove internal input data strobe and add to the output. (CR207678) 
20 //    10/20/05 - Add set & reset check to main  block. (CR219794) 
21 //    10/28/05 - combine strobe block and data block. (CR220298). 
22 //    2/07/06 - Remove set & reset from main block and add specify block (CR225119) 
23 //    2/10/06 - Change Q from reg to wire (CR 225613) 
24 // End Revision 
25  
26 `timescale  1 ps / 1 ps 
27  
28  
29 module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S); 
30  
31     parameter INIT = 1'h0; 
32  
33     output Q; 
34  
35     input  C0, C1, CE, D0, D1, R, S; 
36  
37     wire Q; 
38     reg q_out; 
39  
40     reg q0_out, q1_out; 
41     reg C0_tmp, C1_tmp; 
42  
43     initial begin 
44        q_out = INIT; 
45        q0_out = INIT; 
46        q1_out = INIT; 
47        C0_tmp = 0; 
48        C1_tmp = 0; 
49     end 
50  
51     assign Q = q_out; 
52  
53     always @(posedge C0)  
54       if (CE == 1 || R == 1 || S == 1) begin 
55       C0_tmp <=  1; 
56       C0_tmp <= #100 0; 
57     end 
58  
59     always @(posedge C1)  
60      if (CE == 1 || R == 1 || S == 1) begin 
61       C1_tmp <=  1; 
62       C1_tmp <= #100 0; 
63     end 
64  
65         always @(posedge C0)  
66             if (R) 
67                 q0_out <=  0; 
68             else if (S) 
69                 q0_out <=  1; 
70             else if (CE) 
71                 q0_out <= D0; 
72  
73         always @(posedge C1) 
74             if (R) 
75                 q1_out <=  0; 
76             else if (S) 
77                 q1_out <=  1; 
78             else if (CE) 
79                 q1_out <=  D1; 
80  
81        always @(posedge C0_tmp or posedge C1_tmp ) 
82             if (C1_tmp) 
83                q_out =  q1_out; 
84             else  
85                q_out =  q0_out; 
86  
87     specify 
88         if (R) 
89             (posedge C0 => (Q +: 1'b0)) = (100, 100); 
90         if (!R && S) 
91             (posedge C0 => (Q +: 1'b1)) = (100, 100); 
92         if (!R && !S && CE) 
93             (posedge C0 => (Q +: D0)) = (100, 100); 
94         if (R) 
95             (posedge C1 => (Q +: 1'b0)) = (100, 100); 
96         if (!R && S) 
97             (posedge C1 => (Q +: 1'b1)) = (100, 100); 
98         if (!R && !S && CE) 
99             (posedge C1 => (Q +: D1)) = (100, 100); 
100     endspecify 
101  
102 endmodule