dcm_sp.v

ddr ram controller vhdl code

831         end 
832         else if (clkfb_type == 2'b10) begin 
833             @(posedge CLK2X or rst_in) 
834                 delay_edge = $time; 
835         end 
836         @(posedge clkfb_in or rst_in) begin 
837          fb_delay <= ($time - delay_edge) % period_orig; 
838          fb_delay_found <= 1; 
839        end 
840     end 
841   end 
842  
843 // 
844 // determine feedback lock 
845 // 
846  
847 always @(posedge clkfb_chk or posedge rst_in)  
848   if (rst_in) 
849       clkfb_window <= 0; 
850   else begin 
851       clkfb_window <= 1; 
852     #cycle_jitter clkfb_window <= 0; 
853   end 
854  
855 always @(posedge clkin_fb or posedge rst_in)  
856   if (rst_in) 
857       clkin_window <= 0; 
858   else begin 
859       clkin_window <= 1; 
860     #cycle_jitter clkin_window <= 0; 
861   end 
862  
863 always @(posedge clkin_fb or posedge rst_in)  
864   if (rst_in) 
865      lock_clkin <= 0; 
866   else begin 
867     #1 
868     if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))  
869         lock_clkin <= 1; 
870     else 
871        if (chk_enable==1) 
872          lock_clkin <= 0; 
873   end 
874  
875 always @(posedge clkfb_chk or posedge rst_in)  
876   if (rst_in) 
877     lock_clkfb <= 0; 
878   else begin 
879     #1 
880     if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))   
881         lock_clkfb <= 1; 
882     else 
883        if (chk_enable ==1) 
884         lock_clkfb <= 0; 
885   end 
886  
887 always @(negedge clkin_fb or posedge rst_in)  
888   if (rst_in) 
889     lock_delay <= 0; 
890   else 
891     lock_delay <= lock_clkin || lock_clkfb; 
892  
893 // 
894 // generate lock signal 
895 // 
896  
897 always @(posedge clkin_ps or posedge rst_in)  
898   if (rst_in) begin 
899       lock_out <= 2'b0; 
900       locked_out <=0; 
901   end 
902   else begin 
903     if (clkfb_type == 2'b00) 
904         lock_out[0] <= lock_period; 
905     else 
906         lock_out[0] <= lock_period & lock_delay & lock_fb; 
907     lock_out[1] <= lock_out[0]; 
908     locked_out <= lock_out[1]; 
909   end 
910  
911 always @(negedge clkin_ps or posedge rst_in) 
912   if (rst_in) 
913     lock_out1_neg <= 0; 
914   else 
915     lock_out1_neg <= lock_out[1]; 
916  
917  
918 // 
919 // generate the clk1x_out 
920 // 
921  
922 always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)  
923   if (rst_in)  
924       clk0_out <= 0; 
925   else  
926     if (clkin_ps ==1) 
927        if (clk1x_type==1 && lock_out[0]) begin 
928           clk0_out <= 1; 
929           #(period / 2) 
930              clk0_out <= 0; 
931        end 
932        else 
933           clk0_out <= 1; 
934     else 
935       if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0))) 
936           clk0_out <= 0; 
937  
938 // 
939 // generate the clk2x_out 
940 // 
941  
942 always @(posedge clkin_ps or posedge rst_in)  
943   if (rst_in) 
944      clk2x_out <= 0; 
945   else begin 
946     clk2x_out <= 1; 
947     #(period / 4) 
948     clk2x_out <= 0; 
949         #(period / 4) 
950         clk2x_out <= 1; 
951         #(period / 4) 
952         clk2x_out <= 0; 
953  end 
954  
955 // 
956 // generate the clkdv_out 
957 // 
958  
959 always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) 
960   if (rst_in) begin 
961        clkdv_out <= 1'b0; 
962        clkdv_cnt <= 0; 
963   end 
964   else 
965     if (lock_out1_neg) begin 
966       if (clkdv_cnt >= divide_type -1) 
967            clkdv_cnt <= 0; 
968       else 
969            clkdv_cnt <= clkdv_cnt + 1; 
970  
971       if (clkdv_cnt < divide_type /2) 
972           clkdv_out <= 1'b1; 
973       else 
974          if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0) 
975              clkdv_out <= #(period/4) 1'b0; 
976          else 
977             clkdv_out <= 1'b0; 
978     end 
979  
980  
981 // 
982 // generate fx output signal 
983 // 
984  
985 always @(lock_period or period or denominator or numerator) begin 
986     if (lock_period == 1'b1) begin 
987         period_fx = (period * denominator) / (numerator * 2); 
988         remain_fx = (period * denominator) % (numerator * 2); 
989     end 
990 end 
991  
992 always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in )  
993     if (rst_in == 1)  
994        clkfx_out = 1'b0; 
995     else if (clkin_lost_out == 1'b1 ) begin 
996            if (locked_out == 1) 
997             @(negedge rst_reg[2]); 
998         end 
999     else 
1000       if (lock_out[1] == 1) begin 
1001         clkfx_out = 1'b1; 
1002         for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin 
1003             #(period_fx); 
1004             if (p < remain_fx) 
1005                 #1; 
1006             clkfx_out = !clkfx_out; 
1007         end 
1008         if (period_fx > (period / 2)) begin 
1009             #(period_fx - (period / 2)); 
1010         end 
1011       end 
1012  
1013 // 
1014 // generate all output signal 
1015 // 
1016  
1017 always @(rst_in) 
1018 if (rst_in) begin 
1019    assign CLK0 = 0; 
1020    assign CLK90 = 0; 
1021    assign CLK180 = 0; 
1022    assign CLK270 = 0; 
1023    assign CLK2X = 0; 
1024    assign CLK2X180 =0; 
1025    assign CLKDV = 0; 
1026    assign CLKFX = 0; 
1027    assign CLKFX180 = 0; 
1028 end 
1029 else begin 
1030    deassign CLK0; 
1031    deassign CLK90; 
1032    deassign CLK180; 
1033    deassign CLK270; 
1034    deassign CLK2X; 
1035    deassign CLK2X180; 
1036    deassign CLKDV; 
1037    deassign CLKFX; 
1038    deassign CLKFX180; 
1039 end 
1040  
1041 always @(clk0_out) begin 
1042     CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00); 
1043     CLK90 <= #(clkout_delay + period / 4) clk0_out && !dll_mode_type && (clkfb_type != 2'b00); 
1044     CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00); 
1045     CLK270 <= #(clkout_delay + period / 4) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00); 
1046   end 
1047  
1048 always @(clk2x_out) begin 
1049     CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); 
1050      CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); 
1051 end 
1052  
1053 always @(clkdv_out)  
1054     CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00); 
1055  
1056 always @(clkfx_out ) 
1057     CLKFX <= #(clkout_delay) clkfx_out; 
1058  
1059 always @( clkfx_out or  first_time_locked or locked_out) 
1060   if ( ~first_time_locked) 
1061      CLKFX180 = 0; 
1062   else 
1063      CLKFX180 <=  #(clkout_delay) ~clkfx_out; 
1064  
1065  
1066 endmodule 
1067  
1068 ////////////////////////////////////////////////////// 
1069  
1070 module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst); 
1071 input clock; 
1072 input clock_type; 
1073 input rst; 
1074 output clock_out; 
1075  
1076 reg clock_out; 
1077 reg clock_div2; 
1078 reg [2:0] rst_reg; 
1079 wire clk_src; 
1080  
1081 initial begin 
1082     clock_out = 1'b0; 
1083     clock_div2 = 1'b0; 
1084 end 
1085  
1086 always @(posedge clock)  
1087     clock_div2 <= ~clock_div2; 
1088  
1089 always @(posedge clock) begin 
1090     rst_reg[0] <= rst; 
1091     rst_reg[1] <= rst_reg[0] & rst; 
1092     rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; 
1093 end 
1094  
1095 assign clk_src = (clock_type) ? clock_div2 : clock; 
1096  
1097 always @(clk_src or rst or rst_reg)  
1098     if (rst == 1'b0) 
1099         clock_out = clk_src; 
1100     else if (rst == 1'b1) begin 
1101         clock_out = 1'b0; 
1102         @(negedge rst_reg[2]); 
1103         if (clk_src == 1'b1) 
1104           @(negedge clk_src); 
1105     end 
1106  
1107  
1108 endmodule 
1109  
1110 module dcm_sp_maximum_period_check (clock, rst); 
1111 parameter clock_name = ""; 
1112 parameter maximum_period = 0; 
1113 input clock; 
1114 input rst; 
1115  
1116 time clock_edge; 
1117 time clock_period; 
1118  
1119 initial begin 
1120     clock_edge = 0; 
1121     clock_period = 0; 
1122 end 
1123  
1124 always @(posedge clock) begin 
1125     clock_edge <= $time; 
1126 //    clock_period <= $time - clock_edge; 
1127     clock_period = $time - clock_edge; 
1128     if (clock_period > maximum_period ) begin 
1129         if (rst == 0)  
1130         $display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); 
1131     end 
1132 end 
1133 endmodule 
1134  
1135 module dcm_sp_clock_lost (clock, enable, lost, rst); 
1136 input clock; 
1137 input enable; 
1138 input rst; 
1139 output lost; 
1140  
1141 time clock_edge; 
1142 reg [63:0] period; 
1143 reg clock_low, clock_high; 
1144 reg clock_posedge, clock_negedge; 
1145 reg lost_r, lost_f, lost; 
1146 reg clock_second_pos, clock_second_neg; 
1147  
1148 initial begin 
1149     clock_edge = 0; 
1150     clock_high = 0; 
1151     clock_low = 0; 
1152     lost_r = 0; 
1153     lost_f = 0; 
1154     period = 0; 
1155     clock_posedge = 0; 
1156     clock_negedge = 0; 
1157     clock_second_pos = 0; 
1158     clock_second_neg = 0; 
1159 end 
1160  
1161 always @(posedge clock or posedge rst) 
1162   if (rst==1)  
1163     period <= 0; 
1164   else begin 
1165     clock_edge <= $time; 
1166     if (period != 0 && (($time - clock_edge) <= (1.5 * period))) 
1167         period <= $time - clock_edge; 
1168     else if (period != 0 && (($time - clock_edge) > (1.5 * period))) 
1169         period <= 0; 
1170     else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) 
1171         period <= $time - clock_edge; 
1172   end 
1173  
1174  
1175 always @(posedge clock or posedge rst) 
1176   if (rst)  
1177     lost_r <= 0; 
1178   else  
1179   if (enable == 1 && clock_second_pos == 1) begin 
1180       #1; 
1181       if ( period != 0) 
1182          lost_r <= 0; 
1183       #((period * 9.1) / 10) 
1184       if ((clock_low != 1'b1) && (clock_posedge != 1'b1) && rst == 0) 
1185         lost_r <= 1; 
1186     end 
1187  
1188 always @(posedge clock or negedge clock or posedge rst) 
1189   if (rst) begin 
1190      clock_second_pos <= 0; 
1191      clock_second_neg <= 0; 
1192   end 
1193   else if (clock) 
1194      clock_second_pos <= 1; 
1195   else if (~clock) 
1196      clock_second_neg <= 1; 
1197  
1198 always @(negedge clock or posedge rst) 
1199   if (rst==1) begin 
1200      lost_f <= 0; 
1201    end 
1202    else begin 
1203      if (enable == 1 && clock_second_neg == 1) begin 
1204       if ( period != 0) 
1205         lost_f <= 0; 
1206       #((period * 9.1) / 10) 
1207       if ((clock_high != 1'b1) && (clock_negedge != 1'b1) && rst == 0) 
1208         lost_f <= 1; 
1209     end 
1210   end 
1211  
1212 always @( lost_r or  lost_f or enable) 
1213 begin 
1214   if (enable == 1) 
1215          lost = lost_r | lost_f; 
1216   else 
1217         lost = 0; 
1218 end 
1219  
1220  
1221 always @(posedge clock or negedge clock or posedge rst) 
1222   if (rst==1) begin 
1223            clock_low   <= 1'b0; 
1224            clock_high  <= 1'b0; 
1225            clock_posedge  <= 1'b0; 
1226            clock_negedge <= 1'b0; 
1227   end 
1228   else begin 
1229     if (clock ==1) begin 
1230            clock_low   <= 1'b0; 
1231            clock_high  <= 1'b1; 
1232            clock_posedge  <= 1'b0; 
1233            clock_negedge <= 1'b1; 
1234     end 
1235     else if (clock == 0) begin 
1236            clock_low   <= 1'b1; 
1237            clock_high  <= 1'b0; 
1238            clock_posedge  <= 1'b1; 
1239            clock_negedge <= 1'b0; 
1240     end 
1241 end 
1242  
1243  
1244 endmodule