dcm_sp.v

ddr ram controller vhdl code

416   if ((ps_delay_last >= period_int  && ps_delay < period_int) || 
417        (ps_delay_last >= period_int2  && ps_delay < period_int2) || 
418        (ps_delay_last >= period_int3  && ps_delay < period_int3)) 
419            clkin_ps_mkup_flag = 1; 
420    else  
421            clkin_ps_mkup_flag = 0; 
422 end 
423  
424 always @(posedge clkin_div or negedge clkin_div) begin 
425  if (ps_type == 2'b10) begin 
426   if ((ps_delay_last > 0  && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin  
427      if (clkin_div) begin 
428         clkin_ps_mkup_win <= 1; 
429         clkin_ps_mkup <= 1; 
430         #1; 
431         @(negedge clkin_div) begin 
432            clkin_ps_mkup_win <= 1; 
433            clkin_ps_mkup <= 0; 
434         end 
435      end 
436      else begin 
437         clkin_ps_mkup_win <= 0; 
438         clkin_ps_mkup <= 0; 
439         #1; 
440         @(posedge clkin_div) begin 
441            clkin_ps_mkup_win <= 1; 
442            clkin_ps_mkup <= 1; 
443         end  
444         @(negedge clkin_div) begin 
445            clkin_ps_mkup_win <= 1; 
446            clkin_ps_mkup <= 0; 
447         end 
448      end 
449    end 
450    else begin 
451         clkin_ps_mkup_win <= 0; 
452         clkin_ps_mkup <= 0; 
453    end 
454    ps_delay_last <= ps_delay; 
455  end 
456 end 
457  
458 always @(clkin_ps or lock_fb) 
459     clkin_fb =  clkin_ps & lock_fb; 
460  
461 always @(negedge clkfb_in or posedge rst_in) 
462     if (rst_in) 
463         clkfb_div_en <= 0; 
464     else 
465        if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps) 
466           clkfb_div_en <= 1; 
467  
468 always @(posedge clkfb_in or posedge rst_in) 
469     if (rst_in) 
470         clkfb_div <= 0; 
471     else 
472       if (clkfb_div_en ) 
473         clkfb_div <= ~clkfb_div; 
474  
475 always @(clkfb_in or clkfb_div ) 
476     if (clkfb_type == 2'b10 ) 
477          clkfb_chk = clkfb_div; 
478     else  
479          clkfb_chk = clkfb_in & lock_fb_dly; 
480  
481 always @(posedge clkin_fb or posedge chk_rst) 
482     if (chk_rst) 
483        clkin_chkin <= 0; 
484     else  
485        clkin_chkin <= 1; 
486  
487 always @(posedge clkfb_chk or posedge chk_rst) 
488     if (chk_rst) 
489        clkfb_chkin <= 0; 
490     else  
491        clkfb_chkin <= 1; 
492  
493     assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; 
494     assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 &&  
495                          lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0; 
496  
497 always @(posedge clkin_div or posedge rst_in) 
498   if (rst_in) begin 
499      period_div <= 0; 
500      clkin_div_edge <= 0; 
501    end 
502   else 
503    if ( clkin_div ==1 ) begin 
504       clkin_div_edge <= $time; 
505       if (($time - clkin_div_edge) <= (1.5 * period_div)) 
506           period_div <= $time - clkin_div_edge; 
507       else if ((period_div == 0) && (clkin_div_edge != 0)) 
508           period_div <= $time - clkin_div_edge; 
509    end 
510  
511 always @(posedge clkin_ps or posedge rst_in)  
512   if (rst_in) begin 
513         period_ps <= 0; 
514         clkin_ps_edge <= 0; 
515   end 
516   else  
517   if (clkin_ps == 1 ) begin 
518     clkin_ps_edge <= $time; 
519     if (($time - clkin_ps_edge) <= (1.5 * period_ps)) 
520         period_ps <= $time - clkin_ps_edge; 
521     else if ((period_ps == 0) && (clkin_ps_edge != 0)) 
522         period_ps <= $time - clkin_ps_edge; 
523  end 
524  
525 always @(posedge clkin_ps) begin 
526     lock_ps <= lock_period; 
527     lock_ps_dly <= lock_ps; 
528     lock_fb <= lock_ps_dly; 
529     lock_fb_dly_tmp <= lock_fb; 
530 end 
531  
532 always @(negedge clkin_ps or posedge rst_in)  
533   if (rst_in) 
534     lock_fb_dly <= 1'b0; 
535   else 
536     lock_fb_dly <= #(period/4) lock_fb_dly_tmp; 
537  
538  
539 always @(period or fb_delay ) 
540   if (fb_delay == 0) 
541     clkout_delay = 0; 
542   else 
543     clkout_delay = period - fb_delay; 
544  
545 // 
546 // generate master reset signal 
547 // 
548  
549 always @(posedge clkin_in) begin 
550     rst_reg[0] <= rst_in; 
551     rst_reg[1] <= rst_reg[0] & rst_in; 
552     rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; 
553 end 
554  
555 reg rst_tmp1, rst_tmp2; 
556 initial 
557 begin 
558 rst_tmp1 = 0; 
559 rst_tmp2 = 0; 
560 rst_flag = 0; 
561 end 
562  
563 always @(rst_in)  
564 begin 
565    if (rst_in) 
566        rst_flag = 0; 
567  
568    rst_tmp1 = rst_in; 
569    if (rst_tmp1 == 0 && rst_tmp2 == 1) begin 
570       if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin 
571          rst_flag = 1; 
572         $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); 
573       end 
574    end 
575    rst_tmp2 = rst_tmp1;  
576 end 
577  
578 initial begin 
579     CLK0 = 0; 
580     CLK180 = 0; 
581     CLK270 = 0; 
582     CLK2X = 0; 
583     CLK2X180 = 0; 
584     CLK90 = 0; 
585     CLKDV = 0; 
586     CLKFX = 0; 
587     CLKFX180 = 0; 
588     clk0_out = 0; 
589     clk2x_out = 0; 
590     clkdv_out = 0; 
591     clkdv_cnt = 0; 
592     clkfb_window = 0; 
593     clkfx_out = 0; 
594     clkfx180_en = 0; 
595     clkin_div_edge = 0; 
596     clkin_period[0] = 0; 
597     clkin_period[1] = 0; 
598     clkin_period[2] = 0; 
599     clkin_edge = 0; 
600     clkin_ps_edge = 0; 
601     clkin_window = 0; 
602     clkout_delay = 0; 
603     clock_stopped = 1; 
604     fb_delay  = 0; 
605     fb_delay_found = 0; 
606     lock_clkfb = 0; 
607     lock_clkin = 0; 
608     lock_delay = 0; 
609     lock_fb = 0; 
610     lock_fb_dly = 0; 
611     lock_out = 2'b00; 
612     lock_out1_neg = 0; 
613     lock_period = 0; 
614     lock_ps = 0; 
615     lock_ps_dly = 0; 
616     locked_out = 0; 
617     period = 0; 
618     period_int = 0; 
619     period_int2 = 0; 
620     period_int3 = 0; 
621     period_div = 0; 
622     period_fx = 0; 
623     period_orig = 0; 
624     period_orig_int = 0; 
625     period_ps = 0; 
626     psdone_out = 0; 
627     ps_delay = 0; 
628     ps_delay_md = 0; 
629     ps_delay_init = 0; 
630     ps_acc = 0; 
631     ps_delay_all = 0;  
632     ps_lock = 0; 
633     ps_overflow_out = 0; 
634     ps_overflow_out_ext = 0; 
635     clkin_lost_out_ext = 0; 
636     clkfx_lost_out_ext = 0; 
637     rst_reg = 3'b000; 
638     first_time_locked = 0; 
639     en_status = 0; 
640     clkfb_div = 0; 
641     clkin_chkin = 0; 
642     clkfb_chkin = 0; 
643     clkin_ps_mkup = 0; 
644     clkin_ps_mkup_win = 0; 
645     clkin_ps_mkup_flag = 0; 
646     ps_delay_last = 0; 
647     clkin_ps_tmp = 0; 
648 end 
649  
650 // RST less than 3 cycles, lock = x 
651  
652   assign locked_out_out = (rst_flag) ? 1'bx : locked_out; 
653  
654 // 
655 // detect_first_time_locked 
656 // 
657 always @(posedge locked_out) 
658   if (first_time_locked == 0) 
659           first_time_locked <= 1; 
660  
661 // 
662 // phase shift parameters 
663 // 
664  
665 always @(posedge lock_period)  
666     ps_delay_init <= ps_in * period_orig /256; 
667  
668  
669 always @(period) begin 
670     period_int = period; 
671     if (clkin_type==1) 
672        period_ps_tmp = 2 * period; 
673     else  
674        period_ps_tmp = period; 
675  
676    if (period_ps_tmp > 3000)  
677         ps_max_range = 20 * (period_ps_tmp - 3000)/1000; 
678    else 
679      ps_max_range = 0; 
680 end 
681  
682 always @(ps_delay or rst_in or period_int or lock_period) 
683   if ( rst_in) 
684        ps_delay_md = 0; 
685   else if (lock_period) begin 
686        ps_delay_md =   period_int + ps_delay %  period_int; 
687   end  
688  
689 always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse)  
690   if (rst_in) begin 
691      ps_delay <= 0; 
692      ps_overflow_out <= 0; 
693      ps_acc <= 0; 
694   end 
695   else if (lock_period_pulse)  
696      ps_delay <= ps_delay_init; 
697   else  
698     if (ps_type == 2'b10) 
699         if (psen_in) begin 
700             if (ps_lock == 1) 
701                   $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); 
702             else if (lock_ps)  begin 
703               if (psincdec_in == 1) begin 
704                 if (ps_acc > ps_max_range) 
705                     ps_overflow_out <= 1; 
706                 else begin 
707                     ps_delay <= ps_delay  + PS_STEP; 
708                     ps_acc <= ps_acc + 1; 
709                     ps_overflow_out <= 0; 
710                 end 
711                 ps_lock <= 1; 
712               end 
713               else if (psincdec_in == 0) begin 
714                 if (ps_acc < -ps_max_range) 
715                       ps_overflow_out <= 1; 
716                 else begin 
717                     ps_delay <= ps_delay - PS_STEP; 
718                     ps_acc <= ps_acc - 1; 
719                     ps_overflow_out <= 0; 
720                 end 
721                 ps_lock <= 1; 
722               end 
723            end 
724      end 
725  
726 always @(posedge ps_lock) begin 
727     @(posedge clkin_ps) 
728     @(posedge psclk_in) 
729     @(posedge psclk_in) 
730     @(posedge psclk_in) 
731         psdone_out <= 1; 
732     @(posedge psclk_in) 
733         psdone_out <= 0; 
734         ps_lock <= 0; 
735 end 
736  
737 // 
738 // determine clock period 
739 // 
740  
741 always @(posedge clkin_div or negedge clkin_div or posedge rst_in) 
742   if (rst_in == 1) begin 
743     clkin_period[0] <= 0; 
744     clkin_period[1] <= 0; 
745     clkin_period[2] <= 0; 
746     clkin_edge <= 0; 
747   end 
748   else 
749   if (clkin_div == 1) begin 
750     clkin_edge <= $time; 
751     clkin_period[2] <= clkin_period[1]; 
752     clkin_period[1] <= clkin_period[0]; 
753     if (clkin_edge != 0) 
754         clkin_period[0] <= $time - clkin_edge; 
755   end 
756   else if (clkin_div == 0) 
757       if (lock_period == 1)  
758         if (100000000 < clkin_period[0]/1000) 
759         begin 
760         end 
761         else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin 
762           clkin_period[0] <= clkin_period[1]; 
763         end 
764  
765 always @(negedge clkin_div or posedge rst_in)  
766   if (rst_in == 1) begin 
767       lock_period <= 0; 
768       clock_stopped <= 1; 
769   end 
770   else begin 
771     if (lock_period == 1'b0) begin 
772         if ((clkin_period[0] != 0) && 
773                 (clkin_period[0] - cycle_jitter <= clkin_period[1]) && 
774                 (clkin_period[1] <= clkin_period[0] + cycle_jitter) && 
775                 (clkin_period[1] - cycle_jitter <= clkin_period[2]) && 
776                 (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin 
777             lock_period <= 1; 
778             period_orig <= (clkin_period[0] + 
779                             clkin_period[1] + 
780                             clkin_period[2]) / 3; 
781             period <= clkin_period[0]; 
782         end 
783     end 
784     else if (lock_period == 1'b1) begin 
785         if (100000000 < (clkin_period[0] / 1000)) begin 
786             $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms.  Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); 
787             lock_period <= 0; 
788             @(negedge rst_reg[2]); 
789         end 
790         else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin 
791             clock_stopped <= 1'b1; 
792         end 
793         else if ((clkin_period[0] < period_orig - period_jitter) || 
794                 (period_orig + period_jitter < clkin_period[0])) begin 
795             $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns.  Locked CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); 
796             lock_period <= 0; 
797             @(negedge rst_reg[2]); 
798         end 
799         else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || 
800                 (clkin_period[1] + cycle_jitter < clkin_period[0])) begin 
801             $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns.  Previous CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); 
802             lock_period <= 0; 
803             @(negedge rst_reg[2]); 
804         end 
805         else begin 
806             period <= clkin_period[0]; 
807             clock_stopped <= 1'b0; 
808         end 
809     end 
810 end 
811  
812   assign #1 lock_period_dly1 = lock_period; 
813   assign #(period/2) lock_period_dly = lock_period_dly1; 
814   assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0; 
815  
816 // 
817 // determine clock delay 
818 // 
819  
820 //always @(posedge lock_period or posedge rst_in)  
821 always @(posedge lock_ps_dly or posedge rst_in)  
822   if (rst_in) begin 
823     fb_delay  <= 0; 
824     fb_delay_found <= 0; 
825   end 
826   else begin 
827     if (lock_period && clkfb_type != 2'b00) begin 
828         if (clkfb_type == 2'b01) begin 
829             @(posedge CLK0 or rst_in) 
830                 delay_edge = $time;