dcm_sp.v

ddr ram controller vhdl code

1 // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/DCM_SP.v,v 1.9.4.3 2007/04/11 20:30:19 yanx Exp $ 
2 /////////////////////////////////////////////////////////////////////////////// 
3 // Copyright (c) 1995/2004 Xilinx, Inc. 
4 // All Right Reserved. 
5 /////////////////////////////////////////////////////////////////////////////// 
6 //   ____  ____ 
7 //  /   /\/   / 
8 // /___/  \  /    Vendor : Xilinx 
9 // \   \   \/     Version : 9.2i (J.36) 
10 //  \   \         Description : Xilinx Function Simulation Library Component 
11 //  /   /                  Digital Clock Manager 
12 // /___/   /\     Filename : DCM_SP.v 
13 // \   \  /  \    Timestamp :  
14 //  \___\/\___\ 
15 // 
16 // Revision: 
17 //    02/28/06 - Initial version. 
18 //    05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). 
19 //    06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283). 
20 //    07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). 
21 //               Give warning not support initial phase shifting for variable phase shifting. 
22 //               (CR 235216). 
23 //    09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). 
24 //    12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). 
25 //    04/06/07 - Enable the clock out in clock low time after reset in model  
26 //               clock_divide_by_2  (CR 437471). 
27 // End Revision 
28  
29  
30 `timescale  1 ps / 1 ps 
31  
32 module DCM_SP ( 
33         CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, 
34         CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, 
35         CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); 
36  
37 parameter CLKDV_DIVIDE = 2.0; 
38 parameter integer CLKFX_DIVIDE = 1; 
39 parameter integer CLKFX_MULTIPLY = 4; 
40 parameter CLKIN_DIVIDE_BY_2 = "FALSE"; 
41 parameter CLKIN_PERIOD = 10.0;                  // non-simulatable 
42 parameter CLKOUT_PHASE_SHIFT = "NONE"; 
43 parameter CLK_FEEDBACK = "1X"; 
44 parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable 
45 parameter DFS_FREQUENCY_MODE = "LOW"; 
46 parameter DLL_FREQUENCY_MODE = "LOW"; 
47 parameter DSS_MODE = "NONE";                    // non-simulatable 
48 parameter DUTY_CYCLE_CORRECTION = "TRUE"; 
49 parameter FACTORY_JF = 16'hC080;                // non-simulatable 
50 parameter integer MAXPERCLKIN = 1000000;                // non-modifiable simulation parameter 
51 parameter integer MAXPERPSCLK = 100000000;              // non-modifiable simulation parameter 
52 parameter integer PHASE_SHIFT = 0; 
53 parameter integer SIM_CLKIN_CYCLE_JITTER = 300;         // non-modifiable simulation parameter 
54 parameter integer SIM_CLKIN_PERIOD_JITTER = 1000;       // non-modifiable simulation parameter 
55 parameter STARTUP_WAIT = "FALSE";               // non-simulatable 
56  
57  
58 localparam PS_STEP = 25; 
59  
60 input CLKFB, CLKIN, DSSEN; 
61 input PSCLK, PSEN, PSINCDEC, RST; 
62  
63 output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; 
64 output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; 
65 output [7:0] STATUS; 
66  
67 reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; 
68 reg CLKDV, CLKFX, CLKFX180; 
69  
70 wire locked_out_out; 
71 wire clkfb_in, clkin_in, dssen_in; 
72 wire psclk_in, psen_in, psincdec_in, rst_in; 
73 reg clk0_out; 
74 reg clk2x_out, clkdv_out; 
75 reg clkfx_out, clkfx180_en; 
76 reg rst_flag; 
77 reg locked_out, psdone_out, ps_overflow_out, ps_lock; 
78 reg clkfb_div, clkfb_chk, clkfb_div_en; 
79 integer clkdv_cnt; 
80  
81 reg [1:0] clkfb_type; 
82 reg [8:0] divide_type; 
83 reg clkin_type; 
84 reg [1:0] ps_type; 
85 reg [3:0] deskew_adjust_mode; 
86 reg dfs_mode_type; 
87 reg dll_mode_type; 
88 reg clk1x_type; 
89 integer ps_in; 
90  
91 reg lock_period, lock_delay, lock_clkin, lock_clkfb; 
92 reg first_time_locked; 
93 reg en_status; 
94 reg ps_overflow_out_ext; 
95 reg clkin_lost_out_ext; 
96 reg clkfx_lost_out_ext; 
97 reg [1:0] lock_out; 
98 reg lock_out1_neg; 
99 reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp; 
100 reg fb_delay_found; 
101 reg clock_stopped; 
102 reg clkin_chkin, clkfb_chkin; 
103  
104 wire chk_enable, chk_rst; 
105 wire clkin_div; 
106 wire lock_period_pulse; 
107 wire lock_period_dly, lock_period_dly1; 
108  
109 reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag; 
110 reg clkin_fb; 
111  
112 time FINE_SHIFT_RANGE; 
113 //time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; 
114 integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; 
115 integer ps_delay_last; 
116 integer ps_acc; 
117 time clkin_edge; 
118 time clkin_div_edge; 
119 time clkin_ps_edge; 
120 time delay_edge; 
121 time clkin_period [2:0]; 
122 time period; 
123 integer period_int, period_int2, period_int3, period_ps_tmp; 
124 time period_div; 
125 integer period_orig_int; 
126 time period_orig; 
127 time period_ps; 
128 time clkout_delay; 
129 time fb_delay; 
130 time period_fx, remain_fx; 
131 time period_dv_high, period_dv_low; 
132 time cycle_jitter, period_jitter; 
133  
134 reg clkin_window, clkfb_window; 
135 reg [2:0] rst_reg; 
136 reg [12:0] numerator, denominator, gcd; 
137 reg [23:0] i, n, d, p; 
138  
139 reg notifier; 
140  
141 initial begin 
142     #1; 
143     if ($realtime == 0) begin 
144         $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); 
145         $display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller."); 
146         $finish; 
147     end 
148 end 
149  
150 initial begin 
151     case (2.0) 
152         1.5  : divide_type = 'd3; 
153         2.0  : divide_type = 'd4; 
154         2.5  : divide_type = 'd5; 
155         3.0  : divide_type = 'd6; 
156         3.5  : divide_type = 'd7; 
157         4.0  : divide_type = 'd8; 
158         4.5  : divide_type = 'd9; 
159         5.0  : divide_type = 'd10; 
160         5.5  : divide_type = 'd11; 
161         6.0  : divide_type = 'd12; 
162         6.5  : divide_type = 'd13; 
163         7.0  : divide_type = 'd14; 
164         7.5  : divide_type = 'd15; 
165         8.0  : divide_type = 'd16; 
166         9.0  : divide_type = 'd18; 
167         10.0 : divide_type = 'd20; 
168         11.0 : divide_type = 'd22; 
169         12.0 : divide_type = 'd24; 
170         13.0 : divide_type = 'd26; 
171         14.0 : divide_type = 'd28; 
172         15.0 : divide_type = 'd30; 
173         16.0 : divide_type = 'd32; 
174         default : begin 
175             $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f.  Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); 
176             $finish; 
177         end 
178     endcase 
179  
180     if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin 
181         $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d.  Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); 
182         $finish; 
183     end 
184  
185     if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin 
186         $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d.  Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); 
187         $finish; 
188     end 
189  
190     case (CLKIN_DIVIDE_BY_2) 
191         "false" : clkin_type = 0; 
192         "FALSE" : clkin_type = 0; 
193         "true"  : clkin_type = 1; 
194         "TRUE"  : clkin_type = 1; 
195         default : begin 
196             $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); 
197             $finish; 
198         end 
199     endcase 
200  
201     case (CLKOUT_PHASE_SHIFT) 
202         "NONE"     : begin 
203                          ps_in = 256; 
204                          ps_type = 0; 
205                      end 
206         "none"     : begin 
207                          ps_in = 256; 
208                          ps_type = 0; 
209                      end 
210         "FIXED"    : begin 
211                          ps_in = PHASE_SHIFT + 256; 
212                          ps_type = 1; 
213                      end 
214         "fixed"    : begin 
215                          ps_in = PHASE_SHIFT + 256; 
216                          ps_type = 1; 
217                      end 
218         "VARIABLE" : begin 
219                          ps_in = PHASE_SHIFT + 256; 
220                          ps_type = 2; 
221                      end 
222         "variable" : begin 
223                          ps_in = PHASE_SHIFT + 256; 
224                          ps_type = 2; 
225                          if (PHASE_SHIFT != 0) 
226                              $display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d.  The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT); 
227                      end 
228         default : begin 
229             $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s.  Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT); 
230             $finish; 
231         end 
232     endcase 
233  
234  
235     case (CLK_FEEDBACK) 
236         "none" : clkfb_type = 2'b00; 
237         "NONE" : clkfb_type = 2'b00; 
238         "1x"   : clkfb_type = 2'b01; 
239         "1X"   : clkfb_type = 2'b01; 
240         "2x"   : clkfb_type = 2'b10; 
241         "2X"   : clkfb_type = 2'b10; 
242         default : begin 
243             $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s.  Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK); 
244             $finish; 
245         end 
246     endcase 
247  
248     case (DESKEW_ADJUST) 
249         "source_synchronous" : deskew_adjust_mode = 8; 
250         "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8; 
251         "system_synchronous" : deskew_adjust_mode = 11; 
252         "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; 
253         "0"                  : deskew_adjust_mode = 0; 
254         "1"                  : deskew_adjust_mode = 1; 
255         "2"                  : deskew_adjust_mode = 2; 
256         "3"                  : deskew_adjust_mode = 3; 
257         "4"                  : deskew_adjust_mode = 4; 
258         "5"                  : deskew_adjust_mode = 5; 
259         "6"                  : deskew_adjust_mode = 6; 
260         "7"                  : deskew_adjust_mode = 7; 
261         "8"                  : deskew_adjust_mode = 8; 
262         "9"                  : deskew_adjust_mode = 9; 
263         "10"                 : deskew_adjust_mode = 10; 
264         "11"                 : deskew_adjust_mode = 11; 
265         "12"                 : deskew_adjust_mode = 12; 
266         "13"                 : deskew_adjust_mode = 13; 
267         "14"                 : deskew_adjust_mode = 14; 
268         "15"                 : deskew_adjust_mode = 15; 
269         default : begin 
270             $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s.  Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); 
271             $finish; 
272         end 
273     endcase 
274  
275     case (DFS_FREQUENCY_MODE) 
276         "high" : dfs_mode_type = 1; 
277         "HIGH" : dfs_mode_type = 1; 
278         "low"  : dfs_mode_type = 0; 
279         "LOW"  : dfs_mode_type = 0; 
280         default : begin 
281             $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); 
282             $finish; 
283         end 
284     endcase 
285  
286     period_jitter = SIM_CLKIN_PERIOD_JITTER; 
287     cycle_jitter = SIM_CLKIN_CYCLE_JITTER; 
288  
289     case (DLL_FREQUENCY_MODE) 
290         "high" : dll_mode_type = 1; 
291         "HIGH" : dll_mode_type = 1; 
292         "low"  : dll_mode_type = 0; 
293         "LOW"  : dll_mode_type = 0; 
294         default : begin 
295             $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); 
296             $finish; 
297         end 
298     endcase 
299  
300     if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin 
301             $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s.  CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is  HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK); 
302            $finish; 
303     end  
304  
305     case (DSS_MODE) 
306         "none" : ; 
307         "NONE" : ; 
308         default : begin 
309             $display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute is NONE.", DSS_MODE); 
310             $finish; 
311         end 
312     endcase 
313  
314     case (DUTY_CYCLE_CORRECTION) 
315         "false" : clk1x_type = 0; 
316         "FALSE" : clk1x_type = 0; 
317         "true"  : clk1x_type = 1; 
318         "TRUE"  : clk1x_type = 1; 
319         default : begin 
320             $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); 
321             $finish; 
322         end 
323     endcase 
324  
325     if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin 
326         $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d.  Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); 
327         $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); 
328         $finish; 
329     end 
330  
331     case (STARTUP_WAIT) 
332         "false" : ; 
333         "FALSE" : ; 
334         "true"  : ; 
335         "TRUE"  : ; 
336         default : begin 
337             $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); 
338             $finish; 
339         end 
340     endcase 
341 end 
342  
343 // 
344 // fx parameters 
345 // 
346  
347 initial begin 
348     gcd = 1; 
349     for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin 
350         if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0)) 
351             gcd = i; 
352     end 
353     numerator = CLKFX_MULTIPLY / gcd; 
354     denominator = CLKFX_DIVIDE / gcd; 
355 end 
356  
357 // 
358 // input wire delays 
359 // 
360  
361 buf b_clkin (clkin_in, CLKIN); 
362 buf b_clkfb (clkfb_in, CLKFB); 
363 buf b_dssen (dssen_in, DSSEN); 
364 buf b_psclk (psclk_in, PSCLK); 
365 buf b_psen (psen_in, PSEN); 
366 buf b_psincdec (psincdec_in, PSINCDEC); 
367 buf b_rst (rst_in, RST); 
368 buf #100 b_LOCKED (LOCKED, locked_out_out); 
369 buf #100 b_PSDONE (PSDONE, psdone_out); 
370 buf b_ps_overflow (STATUS[0], ps_overflow_out_ext); 
371 buf b_clkin_lost (STATUS[1], clkin_lost_out_ext); 
372 buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext); 
373  
374 assign STATUS[7:3] = 5'b0; 
375  
376 dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); 
377  
378 dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); 
379 dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); 
380  
381 dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); 
382 dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); 
383  
384 always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out) 
385    if (rst_in == 1 || en_status == 0)  begin 
386        ps_overflow_out_ext = 0; 
387        clkin_lost_out_ext = 0; 
388        clkfx_lost_out_ext = 0; 
389     end 
390    else 
391    begin 
392       ps_overflow_out_ext = ps_overflow_out; 
393       clkin_lost_out_ext = clkin_lost_out; 
394       clkfx_lost_out_ext = clkfx_lost_out; 
395    end 
396  
397 always @(posedge rst_in or posedge LOCKED) 
398   if (rst_in == 1) 
399       en_status <= 0; 
400    else 
401       en_status <= 1; 
402  
403  
404 always @(clkin_div) 
405     clkin_ps_tmp <= #(ps_delay_md) clkin_div; 
406  
407 always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win) 
408   if (clkin_ps_mkup_win) 
409        clkin_ps = clkin_ps_mkup; 
410   else 
411        clkin_ps = clkin_ps_tmp;    
412  
413 always @(ps_delay_last or period_int or ps_delay) begin 
414     period_int2 = 2 * period_int; 
415     period_int3 = 3 * period_int;