ddr.v

ddr ram controller vhdl code

1105      
1106         // Burst terminate 
1107         if (Burst_term === 1'b1) begin 
1108             // Display Debug Message 
1109             if (Debug) begin 
1110                 $display ("At time %t BST  : Burst Terminate",$time); 
1111             end 
1112  
1113             if (Data_in_enable === 1'b1) begin 
1114                 // Illegal to burst terminate a Write 
1115                 $display ("At time %t ERROR: It's illegal to burst terminate a Write", $time); 
1116                 if (!no_halt) $stop (0); 
1117             end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 || 
1118                 // Illegal to burst terminate a Read with Auto Precharge 
1119                 Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin 
1120                 $display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time); 
1121                 if (!no_halt) $stop (0); 
1122             end else begin 
1123                 // Burst Terminate Command Pipeline for Read 
1124                 Cmnd_bst[cas_latency_x2] = 1'b1; 
1125             end 
1126  
1127         end 
1128          
1129         // Read Command 
1130         if (Read_enable === 1'b1) begin 
1131             if (!(power_up_done)) begin 
1132                 $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time); 
1133             end 
1134             // Check for DLL reset before Read 
1135             if (DLL_reset === 1 && DLL_done === 0) begin 
1136                 $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count); 
1137             end 
1138             // Display Debug Message 
1139             if (Debug) begin 
1140                 $display ("At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]}); 
1141             end 
1142  
1143             // Terminate a Write 
1144             if (Data_in_enable === 1'b1) begin 
1145                 Data_in_enable = 1'b0; 
1146             end 
1147  
1148             // Activate to Read without Auto Precharge 
1149             if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) || 
1150                 (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) || 
1151                 (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) || 
1152                 (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin 
1153                 $display("At time %t ERROR: tRCD violation during Read", $time); 
1154             end 
1155  
1156             // Activate to Read with Auto Precharge 
1157             if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) || 
1158                 (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) || 
1159                 (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) || 
1160                 (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin 
1161                 $display ("At time %t ERROR: tRAP violation during Read", $time); 
1162             end 
1163  
1164             // Interrupt a Read with Auto Precharge (same bank only) 
1165             if (Read_precharge [Ba] === 1'b1) begin 
1166                 $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time); 
1167                 if (!no_halt) $stop (0); 
1168                 // Cancel Auto Precharge 
1169                 if (Addr[10] === 1'b0) begin 
1170                     Read_precharge [Ba]= 1'b0; 
1171                 end 
1172             end 
1173             // Activate to Read 
1174             if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || 
1175                 (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin 
1176                 $display("At time %t ERROR: Bank is not Activated for Read", $time); 
1177                 if (!no_halt) $stop (0); 
1178             end else begin 
1179                 // CAS Latency pipeline 
1180                 Read_cmnd[cas_latency_x2] = 1'b1; 
1181                 Read_bank[cas_latency_x2] = Ba; 
1182                 Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; 
1183                 // Auto Precharge 
1184                 if (Addr[10] === 1'b1) begin 
1185                     Read_precharge [Ba]= 1'b1; 
1186                     Count_precharge [Ba]= 0; 
1187                 end 
1188             end 
1189         end 
1190  
1191         // Write Command 
1192         if (Write_enable === 1'b1) begin 
1193             if (!(power_up_done)) begin 
1194                 $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time); 
1195                 if (!no_halt) $stop (0); 
1196             end 
1197             // display debug message 
1198             if (Debug) begin 
1199                 $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}); 
1200             end 
1201  
1202             // Activate to Write 
1203             if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) || 
1204                 (Ba === 2'b01 && $time - RCD_chk1 < tRCD) || 
1205                 (Ba === 2'b10 && $time - RCD_chk2 < tRCD) || 
1206                 (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin 
1207                 $display("At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba); 
1208             end 
1209  
1210             // Read to Write 
1211             if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||  
1212                 Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin 
1213                 if (Data_out_enable || read_precharge_truncation[Ba]) begin 
1214                     $display("At time %t ERROR: Read to Write violation", $time); 
1215                 end 
1216             end 
1217              
1218             // Interrupt a Write with Auto Precharge (same bank only) 
1219             if (Write_precharge [Ba] === 1'b1) begin 
1220                 $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time); 
1221                 if (!no_halt) $stop (0); 
1222                 // Cancel Auto Precharge 
1223                 if (Addr[10] === 1'b0) begin 
1224                     Write_precharge [Ba]= 1'b0; 
1225                 end 
1226             end 
1227             // Activate to Write 
1228             if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || 
1229                 (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin 
1230                 $display("At time %t ERROR: Bank is not Activated for Write", $time); 
1231                 if (!no_halt) $stop (0); 
1232             end else begin 
1233                 // Pipeline for Write 
1234                 Write_cmnd [3] = 1'b1; 
1235                 Write_bank [3] = Ba; 
1236                 Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; 
1237                 // Auto Precharge 
1238                 if (Addr[10] === 1'b1) begin 
1239                     Write_precharge [Ba]= 1'b1; 
1240                     Count_precharge [Ba]= 0; 
1241                 end 
1242             end 
1243         end 
1244     end 
1245     endtask 
1246  
1247     task check_neg_dqs; 
1248     begin 
1249         if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin 
1250             for (i=0; i<DQS_BITS; i=i+1) begin 
1251                 if (expect_neg_dqs[i]) begin 
1252                     $display ("At time %t ERROR: Negative DQS[%1d] transition required.", $time, i); 
1253                 end 
1254                 expect_neg_dqs[i] = 1'b1; 
1255             end 
1256         end else begin 
1257             expect_pos_dqs = 0; 
1258             expect_neg_dqs = 0; 
1259         end 
1260     end 
1261     endtask 
1262  
1263     task check_pos_dqs; 
1264     begin 
1265         if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin 
1266             for (i=0; i<DQS_BITS; i=i+1) begin 
1267                 if (expect_pos_dqs[i]) begin 
1268                     $display ("At time %t ERROR: Positive DQS[%1d] transition required.", $time, i); 
1269                 end 
1270                 expect_pos_dqs[i] = 1'b1; 
1271             end 
1272         end else begin 
1273             expect_pos_dqs = 0; 
1274             expect_neg_dqs = 0; 
1275         end 
1276     end 
1277     endtask 
1278  
1279     // Main Logic 
1280     always @ (posedge Sys_clk) begin 
1281         Manual_Precharge_Pipeline; 
1282         Burst_Terminate_Pipeline; 
1283         Dq_Dqs_Drivers; 
1284         Write_FIFO_DM_Mask_Logic; 
1285         Burst_Decode; 
1286         check_neg_dqs; 
1287         Auto_Precharge_Calculation; 
1288         DLL_Counter; 
1289         Control_Logic; 
1290     end 
1291  
1292     always @ (negedge Sys_clk) begin 
1293         Manual_Precharge_Pipeline; 
1294         Burst_Terminate_Pipeline; 
1295         Dq_Dqs_Drivers; 
1296         Write_FIFO_DM_Mask_Logic; 
1297         Burst_Decode; 
1298         check_pos_dqs; 
1299     end 
1300  
1301     // Dqs Receiver 
1302     always @ (posedge Dqs_in[0]) begin 
1303         // Latch data at posedge Dqs 
1304         dq_rise[7 : 0] = Dq_in[7 : 0]; 
1305         dm_rise[0] = Dm_in[0]; 
1306         expect_pos_dqs[0] = 0; 
1307     end 
1308  
1309     always @ (posedge Dqs_in[1]) begin 
1310         // Latch data at posedge Dqs 
1311         dq_rise[15 : 8] = Dq_in[15 : 8]; 
1312         dm_rise[1] = Dm_in [1]; 
1313         expect_pos_dqs[1] = 0; 
1314     end 
1315  
1316     always @ (negedge Dqs_in[0]) begin 
1317         // Latch data at negedge Dqs 
1318         dq_fall[7 : 0] = Dq_in[7 : 0]; 
1319         dm_fall[0] = Dm_in[0]; 
1320         dm_pair[1:0]  = {dm_rise[0], dm_fall[0]}; 
1321         expect_neg_dqs[0] = 0; 
1322     end 
1323  
1324     always @ (negedge Dqs_in[1]) begin 
1325         // Latch data at negedge Dqs 
1326         dq_fall[15: 8] = Dq_in[15 : 8]; 
1327         dm_fall[1] = Dm_in[1]; 
1328         dm_pair[3:2]  = {dm_rise[1], dm_fall[1]}; 
1329         expect_neg_dqs[1] = 0; 
1330     end 
1331  
1332     specify 
1333                                               // SYMBOL UNITS DESCRIPTION 
1334                                               // ------ ----- ----------- 
1335 //`ifdef sg5B                                   //              specparams for -5B (CL = 3) 
1336 //        specparam tDSS             =     1.0; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK 
1337 //        specparam tDSH             =     1.0; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK 
1338 //        specparam tIH              =   0.600; // tIH    ns    Input Hold Time 
1339 //        specparam tIS              =   0.600; // tIS    ns    Input Setup Time 
1340 //        specparam tDQSH            =    1.75; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK 
1341 //        specparam tDQSL            =    1.75; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK 
1342 //`else `ifdef sg6                              //              specparams for -6 (CL = 2.5) 
1343         specparam tDSS             =     1.2; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK 
1344         specparam tDSH             =     1.2; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK 
1345         specparam tIH              =   0.750; // tIH    ns    Input Hold Time 
1346         specparam tIS              =   0.750; // tIS    ns    Input Setup Time 
1347         specparam tDQSH            =     2.1; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK 
1348         specparam tDQSL            =     2.1; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK 
1349 //`else `ifdef sg75E                            //              specparams for -75E (CL = 2) 
1350 //        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK 
1351 //        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK 
1352 //        specparam tIH              =   0.900; // tIH    ns    Input Hold Time 
1353 //        specparam tIS              =   0.900; // tIS    ns    Input Setup Time 
1354 //        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK 
1355 //        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK 
1356 //`else  
1357 //`define sg75Z                           //              specparams for -75Z (CL = 2) 
1358 //        specparam tDSS             =     1.5; // tDSS   ns    DQS falling edge to CLK rising (setup time) = 0.2*tCK 
1359 //        specparam tDSH             =     1.5; // tDSH   ns    DQS falling edge from CLK rising (hold time) = 0.2*tCK 
1360 //        specparam tIH              =   0.900; // tIH    ns    Input Hold Time 
1361 //        specparam tIS              =   0.900; // tIS    ns    Input Setup Time 
1362 //        specparam tDQSH            =   2.625; // tDQSH  ns    DQS input High Pulse Width = 0.35*tCK 
1363 //        specparam tDQSL            =   2.625; // tDQSL  ns    DQS input Low Pulse Width = 0.35*tCK 
1364 //`endif `endif `endif 
1365         $width    (posedge Dqs_in[0] &&& wdqs_valid, tDQSH); 
1366         $width    (posedge Dqs_in[1] &&& wdqs_valid, tDQSH); 
1367         $width    (negedge Dqs_in[0] &&& wdqs_valid, tDQSL); 
1368         $width    (negedge Dqs_in[1] &&& wdqs_valid, tDQSL); 
1369         $setuphold(posedge Clk,   Cke,   tIS, tIH); 
1370         $setuphold(posedge Clk,   Cs_n,  tIS, tIH); 
1371         $setuphold(posedge Clk,   Cas_n, tIS, tIH); 
1372         $setuphold(posedge Clk,   Ras_n, tIS, tIH); 
1373         $setuphold(posedge Clk,   We_n,  tIS, tIH); 
1374         $setuphold(posedge Clk,   Addr,  tIS, tIH); 
1375         $setuphold(posedge Clk,   Ba,    tIS, tIH); 
1376         $setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH); 
1377     endspecify 
1378  
1379 endmodule