ddr.v

ddr ram controller vhdl code

553         Write_cmnd [2] = Write_cmnd [3]; 
554         Write_cmnd [3] = 1'b0; 
555  
556         // Write command pipeline 
557         Write_bank [0] = Write_bank [1]; 
558         Write_bank [1] = Write_bank [2]; 
559         Write_bank [2] = Write_bank [3]; 
560         Write_bank [3] = 2'b0; 
561  
562         // Write column pipeline 
563         Write_cols [0] = Write_cols [1]; 
564         Write_cols [1] = Write_cols [2]; 
565         Write_cols [2] = Write_cols [3]; 
566         Write_cols [3] = {COL_BITS{1'b0}}; 
567  
568         // Initialize Write command 
569         if (Write_cmnd [0] === 1'b1) begin 
570             Data_in_enable = 1'b1; 
571             Bank_addr = Write_bank [0]; 
572             Cols_addr = Write_cols [0]; 
573             Cols_brst = Cols_addr [2 : 0]; 
574             Burst_counter = 0; 
575  
576             // Row address mux 
577             case (Bank_addr) 
578                 2'd0    : Rows_addr = B0_row_addr; 
579                 2'd1    : Rows_addr = B1_row_addr; 
580                 2'd2    : Rows_addr = B2_row_addr; 
581                 2'd3    : Rows_addr = B3_row_addr; 
582                 default : $display ("At time %t ERROR: Invalid Row Address", $time); 
583             endcase 
584         end 
585  
586         // Write data 
587         if (Data_in_enable === 1'b1) begin 
588  
589             // Data Buffer 
590             read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); 
591  
592             // write negedge Dqs on posedge Sys_clk 
593             if (Sys_clk) begin 
594                 if (!dm_fall[0]) begin 
595                     Dq_buf [ 7 : 0] = dq_fall [ 7 : 0]; 
596                 end 
597                 if (!dm_fall[1]) begin 
598                     Dq_buf [15 : 8] = dq_fall [15 : 8]; 
599                 end 
600                 if (~&dm_fall) begin 
601                     if (Debug) begin 
602                         $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); 
603                     end 
604                 end 
605             // write posedge Dqs on negedge Sys_clk 
606             end else begin 
607                 if (!dm_rise[0]) begin 
608                     Dq_buf [ 7 : 0] = dq_rise [ 7 : 0]; 
609                 end 
610                 if (!dm_rise[1]) begin 
611                     Dq_buf [15 : 8] = dq_rise [15 : 8]; 
612                 end 
613                 if (~&dm_rise) begin 
614                     if (Debug) begin 
615                         $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); 
616                     end 
617                 end 
618             end 
619  
620             // Write Data 
621             write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); 
622  
623             // tWR start and tWTR check 
624             if (Sys_clk && &dm_pair === 1'b0)  begin 
625                 case (Bank_addr) 
626                     2'd0    : WR_chk0 = $time; 
627                     2'd1    : WR_chk1 = $time; 
628                     2'd2    : WR_chk2 = $time; 
629                     2'd3    : WR_chk3 = $time; 
630                     default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time); 
631                 endcase 
632  
633                 // tWTR check 
634                 if (Read_enable === 1'b1) begin 
635                     $display ("At time %t ERROR: tWTR violation during Read", $time); 
636                 end 
637             end 
638         end 
639     end 
640     endtask 
641  
642     // Auto Precharge Calculation 
643     task Auto_Precharge_Calculation; 
644     begin 
645         // Precharge counter 
646         if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin 
647             Count_precharge [0] = Count_precharge [0] + 1; 
648         end 
649         if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin 
650             Count_precharge [1] = Count_precharge [1] + 1; 
651         end 
652         if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin 
653             Count_precharge [2] = Count_precharge [2] + 1; 
654         end 
655         if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin 
656             Count_precharge [3] = Count_precharge [3] + 1; 
657         end 
658  
659         // Read with AutoPrecharge Calculation 
660         //      The device start internal precharge when: 
661         //          1.  Meet tRAS requirement 
662         //          2.  BL/2 cycles after command 
663         if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin 
664             if (Count_precharge[0] >= burst_length/2) begin 
665                 Pc_b0 = 1'b1; 
666                 Act_b0 = 1'b0; 
667                 RP_chk0 = $time; 
668                 Read_precharge[0] = 1'b0; 
669             end 
670         end 
671         if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin 
672             if (Count_precharge[1] >= burst_length/2) begin 
673                 Pc_b1 = 1'b1; 
674                 Act_b1 = 1'b0; 
675                 RP_chk1 = $time; 
676                 Read_precharge[1] = 1'b0; 
677             end 
678         end 
679         if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin 
680             if (Count_precharge[2] >= burst_length/2) begin 
681                 Pc_b2 = 1'b1; 
682                 Act_b2 = 1'b0; 
683                 RP_chk2 = $time; 
684                 Read_precharge[2] = 1'b0; 
685             end 
686         end 
687         if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin 
688             if (Count_precharge[3] >= burst_length/2) begin 
689                 Pc_b3 = 1'b1; 
690                 Act_b3 = 1'b0; 
691                 RP_chk3 = $time; 
692                 Read_precharge[3] = 1'b0; 
693             end 
694         end 
695  
696         // Write with AutoPrecharge Calculation 
697         //      The device start internal precharge when: 
698         //          1.  Meet tRAS requirement 
699         //          2.  Write Latency PLUS BL/2 cycles PLUS tWR after Write command 
700  
701         if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin  
702             if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin 
703                 Pc_b0 = 1'b1; 
704                 Act_b0 = 1'b0; 
705                 RP_chk0 = $time; 
706                 Write_precharge[0] = 1'b0; 
707             end 
708         end 
709         if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin  
710             if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin 
711                 Pc_b1 = 1'b1; 
712                 Act_b1 = 1'b0; 
713                 RP_chk1 = $time; 
714                 Write_precharge[1] = 1'b0; 
715             end 
716         end 
717         if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin  
718             if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin 
719                 Pc_b2 = 1'b1; 
720                 Act_b2 = 1'b0; 
721                 RP_chk2 = $time; 
722                 Write_precharge[2] = 1'b0; 
723             end 
724         end 
725         if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin  
726             if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin 
727                 Pc_b3 = 1'b1; 
728                 Act_b3 = 1'b0; 
729                 RP_chk3 = $time; 
730                 Write_precharge[3] = 1'b0; 
731             end 
732         end 
733     end 
734     endtask 
735  
736     // DLL Counter 
737     task DLL_Counter; 
738     begin 
739         if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin 
740             DLL_count = DLL_count + 1; 
741             if (DLL_count >= 200) begin 
742                 DLL_done = 1'b1; 
743             end 
744         end 
745     end 
746     endtask 
747  
748     // Control Logic 
749     task Control_Logic; 
750     begin 
751         // Auto Refresh 
752         if (Aref_enable === 1'b1) begin 
753             // Display Debug Message 
754             if (Debug) begin 
755                 $display ("At time %t AREF : Auto Refresh", $time); 
756             end 
757              
758             // Precharge to Auto Refresh 
759             if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || 
760                 ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin 
761                 $display ("At time %t ERROR: tRP violation during Auto Refresh", $time); 
762             end 
763              
764             // LMR/EMR to Auto Refresh 
765             if ($time - MRD_chk < tMRD) begin 
766                 $display ("At time %t ERROR: tMRD violation during Auto Refresh", $time); 
767             end 
768  
769             // Auto Refresh to Auto Refresh 
770             if ($time - RFC_chk < tRFC) begin 
771                 $display ("At time %t ERROR: tRFC violation during Auto Refresh", $time); 
772             end 
773              
774             // Precharge to Auto Refresh 
775             if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin 
776                 $display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time); 
777                 if (!no_halt) $stop (0); 
778             end else begin 
779                 aref_count = aref_count + 1; 
780                 RFC_chk = $time; 
781             end 
782         end 
783      
784         // Extended Mode Register 
785         if (Ext_mode_enable === 1'b1) begin 
786             if (Debug) begin 
787                 $display ("At time %t EMR  : Extended Mode Register", $time); 
788             end 
789  
790             // Precharge to LMR/EMR 
791             if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || 
792                 ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin 
793                 $display ("At time %t ERROR: tRP violation during Extended Mode Register", $time); 
794             end 
795  
796             // LMR/EMR to LMR/EMR 
797             if ($time - MRD_chk < tMRD) begin 
798                 $display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time); 
799             end 
800  
801             // Auto Refresh to LMR/EMR 
802             if ($time - RFC_chk < tRFC) begin 
803                 $display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time); 
804             end 
805  
806             // Precharge to LMR/EMR 
807             if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin 
808                 $display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time); 
809                 if (!no_halt) $stop (0); 
810             end else begin 
811                 if (Addr[0] === 1'b0) begin 
812                     DLL_enable = 1'b1; 
813                     if (Debug) begin 
814                         $display ("At time %t EMR  : Enable DLL", $time); 
815                     end 
816                 end else begin 
817                     DLL_enable = 1'b0; 
818                     if (Debug) begin 
819                         $display ("At time %t EMR  : Disable DLL", $time); 
820                     end 
821                 end 
822                 MRD_chk = $time; 
823             end 
824         end 
825      
826         // Load Mode Register 
827         if (Mode_reg_enable === 1'b1) begin 
828             if (Debug) begin