ddr.v

ddr ram controller vhdl code

277     end 
278  
279     // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high 
280     always @(Cke) begin 
281         if (Cke === 1'b1) begin 
282             if (!((Cs_n) || (~Cs_n &  Ras_n & Cas_n &  We_n))) begin 
283                 $display ("%m: at time %t MEMORY ERROR:  You must have a Deselect or NOP command applied", $time); 
284                 $display ("%m:           when the Clock Enable is brought High."); 
285             end  
286         end 
287     end 
288  
289     // Check the initialization sequence 
290     initial begin 
291         @ (posedge Cke) begin 
292             @ (posedge DLL_enable) begin 
293                 aref_count = 0; 
294                 @ (posedge DLL_reset) begin 
295                     @ (Prech_count) begin 
296                         if (aref_count >= 2) begin 
297                             if (Debug) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time); 
298                             power_up_done = 1; 
299                         end else begin 
300                             aref_count = 0; 
301                             @ (aref_count >= 2) begin 
302                                 if (Debug) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time); 
303                                 power_up_done = 1; 
304                             end 
305                         end 
306                     end 
307                 end 
308             end 
309         end 
310     end 
311  
312     // Write Memory 
313     task write_mem; 
314         input [full_mem_bits - 1 : 0] addr; 
315         input       [DQ_BITS - 1 : 0] data; 
316         reg       [part_mem_bits : 0] i; 
317         begin 
318 `ifdef FULL_MEM 
319             mem_array[addr] = data; 
320 `else 
321             begin : loop 
322                 for (i = 0; i < mem_used; i = i + 1) begin 
323                     if (addr_array[i] === addr) begin 
324                         disable loop; 
325                     end 
326                 end 
327             end 
328             if (i === mem_used) begin 
329                 if (i === (1<<part_mem_bits)) begin 
330                     $display ("At time %t ERROR: Memory overflow.\n  Write to Address %h with Data %h will be lost.\n  You must increase the part_mem_bits parameter or define FULL_MEM.", $time, addr, data); 
331                 end else begin 
332                     mem_used = mem_used + 1; 
333                     addr_array[i] = addr; 
334                 end 
335             end 
336             mem_array[i] = data; 
337 `endif 
338         end 
339     endtask 
340  
341     // Read Memory 
342     task read_mem; 
343         input [full_mem_bits - 1 : 0] addr; 
344         output      [DQ_BITS - 1 : 0] data; 
345         reg       [part_mem_bits : 0] i; 
346         begin 
347 `ifdef FULL_MEM 
348             data = mem_array[addr]; 
349 `else 
350             begin : loop 
351                 for (i = 0; i < mem_used; i = i + 1) begin 
352                     if (addr_array[i] === addr) begin 
353                         disable loop; 
354                     end 
355                 end 
356             end 
357             if (i <= mem_used) begin 
358                 data = mem_array[i]; 
359             end 
360 `endif 
361         end 
362     endtask 
363  
364     // Burst Decode 
365     task Burst_Decode; 
366     begin 
367  
368         // Advance Burst Counter 
369         if (Burst_counter < burst_length) begin 
370             Burst_counter = Burst_counter + 1; 
371         end 
372  
373         // Burst Type 
374         if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst 
375             Cols_temp = Cols_addr + 1; 
376         end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst 
377             Cols_temp[2] =  Burst_counter[2] ^ Cols_brst[2]; 
378             Cols_temp[1] =  Burst_counter[1] ^ Cols_brst[1]; 
379             Cols_temp[0] =  Burst_counter[0] ^ Cols_brst[0]; 
380         end 
381  
382         // Burst Length 
383         if (burst_length === 2) begin 
384             Cols_addr [0] = Cols_temp [0]; 
385         end else if (burst_length === 4) begin 
386             Cols_addr [1 : 0] = Cols_temp [1 : 0]; 
387         end else if (burst_length === 8) begin 
388             Cols_addr [2 : 0] = Cols_temp [2 : 0]; 
389         end else begin 
390             Cols_addr = Cols_temp; 
391         end 
392  
393         // Data Counter 
394         if (Burst_counter >= burst_length) begin 
395             Data_in_enable = 1'b0; 
396             Data_out_enable = 1'b0; 
397             read_precharge_truncation = 4'h0; 
398         end 
399          
400     end 
401     endtask 
402  
403     // Manual Precharge Pipeline 
404     task Manual_Precharge_Pipeline; 
405     begin 
406         // A10 Precharge Pipeline 
407         A10_precharge[0] = A10_precharge[1]; 
408         A10_precharge[1] = A10_precharge[2]; 
409         A10_precharge[2] = A10_precharge[3]; 
410         A10_precharge[3] = A10_precharge[4]; 
411         A10_precharge[4] = A10_precharge[5]; 
412         A10_precharge[5] = A10_precharge[6]; 
413         A10_precharge[6] = 1'b0; 
414  
415         // Bank Precharge Pipeline 
416         Bank_precharge[0] = Bank_precharge[1]; 
417         Bank_precharge[1] = Bank_precharge[2]; 
418         Bank_precharge[2] = Bank_precharge[3]; 
419         Bank_precharge[3] = Bank_precharge[4]; 
420         Bank_precharge[4] = Bank_precharge[5]; 
421         Bank_precharge[5] = Bank_precharge[6]; 
422         Bank_precharge[6] = 2'b0; 
423  
424         // Command Precharge Pipeline 
425         Cmnd_precharge[0] = Cmnd_precharge[1]; 
426         Cmnd_precharge[1] = Cmnd_precharge[2]; 
427         Cmnd_precharge[2] = Cmnd_precharge[3]; 
428         Cmnd_precharge[3] = Cmnd_precharge[4]; 
429         Cmnd_precharge[4] = Cmnd_precharge[5]; 
430         Cmnd_precharge[5] = Cmnd_precharge[6]; 
431         Cmnd_precharge[6] = 1'b0; 
432  
433         // Terminate a Read if same bank or all banks 
434         if (Cmnd_precharge[0] === 1'b1) begin 
435             if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin 
436                 if (Data_out_enable === 1'b1) begin 
437                     Data_out_enable = 1'b0; 
438                     read_precharge_truncation = 4'hF; 
439                 end 
440             end 
441         end 
442     end 
443     endtask 
444  
445     // Burst Terminate Pipeline 
446     task Burst_Terminate_Pipeline; 
447     begin 
448         // Command Precharge Pipeline 
449         Cmnd_bst[0] = Cmnd_bst[1]; 
450         Cmnd_bst[1] = Cmnd_bst[2]; 
451         Cmnd_bst[2] = Cmnd_bst[3]; 
452         Cmnd_bst[3] = Cmnd_bst[4]; 
453         Cmnd_bst[4] = Cmnd_bst[5]; 
454         Cmnd_bst[5] = Cmnd_bst[6]; 
455         Cmnd_bst[6] = 1'b0; 
456  
457         // Terminate a Read regardless of banks 
458         if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin 
459             Data_out_enable = 1'b0; 
460         end 
461     end 
462     endtask 
463  
464     // Dq and Dqs Drivers 
465     task Dq_Dqs_Drivers; 
466     begin 
467         // read command pipeline 
468         Read_cmnd [0] = Read_cmnd [1]; 
469         Read_cmnd [1] = Read_cmnd [2]; 
470         Read_cmnd [2] = Read_cmnd [3]; 
471         Read_cmnd [3] = Read_cmnd [4]; 
472         Read_cmnd [4] = Read_cmnd [5]; 
473         Read_cmnd [5] = Read_cmnd [6]; 
474         Read_cmnd [6] = 1'b0; 
475  
476         // read bank pipeline 
477         Read_bank [0] = Read_bank [1]; 
478         Read_bank [1] = Read_bank [2]; 
479         Read_bank [2] = Read_bank [3]; 
480         Read_bank [3] = Read_bank [4]; 
481         Read_bank [4] = Read_bank [5]; 
482         Read_bank [5] = Read_bank [6]; 
483         Read_bank [6] = 2'b0; 
484  
485         // read column pipeline 
486         Read_cols [0] = Read_cols [1]; 
487         Read_cols [1] = Read_cols [2]; 
488         Read_cols [2] = Read_cols [3]; 
489         Read_cols [3] = Read_cols [4]; 
490         Read_cols [4] = Read_cols [5]; 
491         Read_cols [5] = Read_cols [6]; 
492         Read_cols [6] = 0; 
493  
494         // Initialize Read command 
495         if (Read_cmnd [0] === 1'b1) begin 
496             Data_out_enable = 1'b1; 
497             Bank_addr = Read_bank [0]; 
498             Cols_addr = Read_cols [0]; 
499             Cols_brst = Cols_addr [2 : 0]; 
500             Burst_counter = 0; 
501  
502             // Row Address Mux 
503             case (Bank_addr) 
504                 2'd0    : Rows_addr = B0_row_addr; 
505                 2'd1    : Rows_addr = B1_row_addr; 
506                 2'd2    : Rows_addr = B2_row_addr; 
507                 2'd3    : Rows_addr = B3_row_addr; 
508                 default : $display ("At time %t ERROR: Invalid Bank Address", $time); 
509             endcase 
510         end 
511  
512         // Toggle Dqs during Read command 
513         if (Data_out_enable === 1'b1) begin 
514             Dqs_int = 1'b0; 
515             if (Dqs_out === {DQS_BITS{1'b0}}) begin 
516                 Dqs_out = {DQS_BITS{1'b1}}; 
517             end else if (Dqs_out === {DQS_BITS{1'b1}}) begin 
518                 Dqs_out = {DQS_BITS{1'b0}}; 
519             end else begin 
520                 Dqs_out = {DQS_BITS{1'b0}}; 
521             end 
522         end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin 
523             Dqs_out = {DQS_BITS{1'bz}}; 
524         end 
525  
526         // Initialize dqs for Read command 
527         if (Read_cmnd [2] === 1'b1) begin 
528             if (Data_out_enable === 1'b0) begin 
529                 Dqs_int = 1'b1; 
530                 Dqs_out = {DQS_BITS{1'b0}}; 
531             end 
532         end 
533  
534         // Read latch 
535         if (Data_out_enable === 1'b1) begin 
536             // output data 
537             read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out); 
538             if (Debug) begin 
539                 $display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out); 
540             end 
541         end else begin 
542             Dq_out = {DQ_BITS{1'bz}}; 
543         end 
544     end 
545     endtask 
546  
547     // Write FIFO and DM Mask Logic 
548     task Write_FIFO_DM_Mask_Logic; 
549     begin 
550         // Write command pipeline 
551         Write_cmnd [0] = Write_cmnd [1]; 
552         Write_cmnd [1] = Write_cmnd [2];