ddr.v

ddr ram controller vhdl code

1 /**************************************************************************************** 
2 * 
3 *    File Name:  ddr.v 
4 *      Version:  5.7 
5 *        Model:  BUS Functional 
6 * 
7 * Dependencies:  ddr_parameters.v 
8 * 
9 *  Description:  Micron SDRAM DDR (Double Data Rate) 
10 * 
11 *   Limitation:  - Doesn't check for 8K-cycle refresh. 
12 *                - Doesn't check power-down entry/exit 
13 *                - Doesn't check self-refresh entry/exit. 
14 * 
15 *         Note:  - Set simulator resolution to "ps" accuracy 
16 *                - Set Debug = 0 to disable $display messages 
17 *                - Model assume Clk and Clk# crossing at both edge 
18 * 
19 *   Disclaimer   This software code and all associated documentation, comments or other  
20 *  of Warranty:  information (collectively "Software") is provided "AS IS" without  
21 *                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY  
22 *                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED  
23 *                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES  
24 *                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT  
25 *                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE  
26 *                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.  
27 *                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR  
28 *                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,  
29 *                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE  
30 *                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,  
31 *                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,  
32 *                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,  
33 *                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,  
34 *                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE  
35 *                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH  
36 *                DAMAGES. Because some jurisdictions prohibit the exclusion or  
37 *                limitation of liability for consequential or incidental damages, the  
38 *                above limitation may not apply to you. 
39 * 
40 *                Copyright 2003 Micron Technology, Inc. All rights reserved. 
41 * 
42 * Rev  Author Date        Changes 
43 * ---  ------ ----------  --------------------------------------- 
44 * 2.1  SPH    03/19/2002  - Second Release 
45 *                         - Fix tWR and several incompatability 
46 *                           between different simulators 
47 * 3.0  TFK    02/18/2003  - Added tDSS and tDSH timing checks. 
48 *                         - Added tDQSH and tDQSL timing checks. 
49 * 3.1  CAH    05/28/2003  - update all models to release version 3.1 
50 *                           (no changes to this model) 
51 * 3.2  JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3 
52 * 3.3  JMK    09/11/2003  - Added initialization sequence checks. 
53 * 4.0  JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v" 
54 *                         - Fixed tWTR check 
55 * 4.1  JMK    01/14/2004  - Grouped specify parameters by speed grade 
56 *                         - Fixed mem_sizes parameter 
57 * 4.2  JMK    03/19/2004  - Fixed pulse width checking on Dqs 
58 * 4.3  JMK    04/27/2004  - Changed BL wire size in tb module 
59 *                         - Changed Dq_buf size to [15:0] 
60 * 5.0  JMK    06/16/2004  - Added read to write checking. 
61 *                         - Added read with precharge truncation to write checking. 
62 *                         - Added associative memory array to reduce memory consumption. 
63 *                         - Added checking for required DQS edges during write. 
64 * 5.1  JMK    08/16/2004  - Fixed checking for required DQS edges during write. 
65 *                         - Fixed wdqs_valid window. 
66 * 5.2  JMK    09/24/2004  - Read or Write without activate will be ignored. 
67 * 5.3  JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate. 
68 *                         - Added tRFC checking during Load Mode and Precharge. 
69 * 5.4  JMK    12/13/2004  - The model will not respond to illegal command sequences. 
70 * 5.5  SPH    01/13/2005  - The model will issue a halt on illegal command sequences. 
71 *      JMK    02/11/2005  - Changed the display format for numbers to hex. 
72 * 5.6  JMK    04/22/2005  - Fixed Write with auto precharge calculation. 
73 * 5.7  JMK    08/05/2005  - Changed conditions for read with precharge truncation error. 
74 *                         - Renamed parameters file with .vh extension. 
75 ****************************************************************************************/ 
76  
77 // DO NOT CHANGE THE TIMESCALE 
78 // MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION 
79 `timescale 1ns / 1ps 
80  
81 module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); 
82  
83     `include "ddr_parameters.vh" 
84  
85     // Port Declarations 
86     inout       [DQ_BITS - 1 : 0] Dq; 
87     inout      [DQS_BITS - 1 : 0] Dqs; 
88     input     [ADDR_BITS - 1 : 0] Addr; 
89     input                 [1 : 0] Ba; 
90     input                         Clk; 
91     input                         Clk_n; 
92     input                         Cke; 
93     input                         Cs_n; 
94     input                         Ras_n; 
95     input                         Cas_n; 
96     input                         We_n; 
97     input       [DM_BITS - 1 : 0] Dm; 
98  
99     // Internal Wires (fixed width) 
100     wire                 [15 : 0] Dq_in; 
101     wire                  [1 : 0] Dqs_in; 
102     wire                  [1 : 0] Dm_in; 
103      
104     assign Dq_in   [DQ_BITS - 1 : 0] = Dq; 
105     assign Dqs_in [DQS_BITS - 1 : 0] = Dqs; 
106     assign Dm_in   [DM_BITS - 1 : 0] = Dm; 
107  
108     // Data pair 
109     reg                  [15 : 0] dq_rise; 
110     reg                   [1 : 0] dm_rise; 
111     reg                  [15 : 0] dq_fall; 
112     reg                   [1 : 0] dm_fall; 
113     reg                   [3 : 0] dm_pair; 
114     reg                  [15 : 0] Dq_buf; 
115      
116     // Mode Register 
117     reg       [ADDR_BITS - 1 : 0] Mode_reg; 
118  
119     // Internal System Clock 
120     reg                           CkeZ, Sys_clk; 
121  
122     // Internal Dqs initialize 
123     reg                           Dqs_int; 
124  
125     // Dqs buffer 
126     reg        [DQS_BITS - 1 : 0] Dqs_out; 
127  
128     // Dq buffer 
129     reg         [DQ_BITS - 1 : 0] Dq_out; 
130  
131     // Read pipeline variables 
132     reg                           Read_cmnd [0 : 6]; 
133     reg                   [1 : 0] Read_bank [0 : 6]; 
134     reg        [COL_BITS - 1 : 0] Read_cols [0 : 6]; 
135  
136     // Write pipeline variables 
137     reg                           Write_cmnd [0 : 3]; 
138     reg                   [1 : 0] Write_bank [0 : 3]; 
139     reg        [COL_BITS - 1 : 0] Write_cols [0 : 3]; 
140  
141     // Auto precharge variables 
142     reg                           Read_precharge  [0 : 3]; 
143     reg                           Write_precharge [0 : 3]; 
144     integer                       Count_precharge [0 : 3]; 
145  
146     // Manual precharge variables 
147     reg                           A10_precharge  [0 : 6]; 
148     reg                   [1 : 0] Bank_precharge [0 : 6]; 
149     reg                           Cmnd_precharge [0 : 6]; 
150  
151     // Burst terminate variables 
152     reg                           Cmnd_bst [0 : 6]; 
153  
154     // Memory Banks 
155 `ifdef FULL_MEM 
156     reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1]; 
157 `else 
158     reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1]; 
159     reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1]; 
160     reg   [part_mem_bits     : 0] mem_used; 
161     initial mem_used = 0; 
162 `endif 
163  
164     // Dqs edge checking 
165     integer i; 
166     reg  [1:0] expect_pos_dqs; 
167     reg  [1:0] expect_neg_dqs; 
168  
169     // Burst counter 
170     reg        [COL_BITS - 1 : 0] Burst_counter; 
171  
172     // Precharge variables 
173     reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3; 
174  
175     // Activate variables 
176     reg                           Act_b0, Act_b1, Act_b2, Act_b3; 
177  
178     // Data IO variables 
179     reg                           Data_in_enable; 
180     reg                           Data_out_enable; 
181  
182     // Internal address mux variables 
183     reg                   [1 : 0] Prev_bank; 
184     reg                   [1 : 0] Bank_addr; 
185     reg        [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp; 
186     reg       [ADDR_BITS - 1 : 0] Rows_addr; 
187     reg       [ADDR_BITS - 1 : 0] B0_row_addr; 
188     reg       [ADDR_BITS - 1 : 0] B1_row_addr; 
189     reg       [ADDR_BITS - 1 : 0] B2_row_addr; 
190     reg       [ADDR_BITS - 1 : 0] B3_row_addr; 
191  
192     // DLL Reset variable 
193     reg                           DLL_enable; 
194     reg                           DLL_reset; 
195     reg                           DLL_done; 
196     integer                       DLL_count; 
197     integer                       aref_count; 
198     integer                       Prech_count; 
199     reg                           power_up_done; 
200  
201     // Write DQS for tDSS, tDSH, tDQSH, tDQSL checks 
202     wire      wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable; 
203  
204     // Commands Decode 
205     wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n; 
206     wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n; 
207     wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n; 
208     wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1]; 
209     wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1]; 
210     wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n; 
211     wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n; 
212     wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n; 
213  
214     // Burst Length Decode 
215     wire [3:0] burst_length = 1 << (Mode_reg[2:0]); 
216     reg  [3:0] read_precharge_truncation; 
217  
218     // CAS Latency Decode 
219 //    wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4]; 
220     wire [2:0] cas_latency_x2 = 5; 
221  
222     // DQS Buffer 
223     assign    Dqs = Dqs_out; 
224  
225     // DQ Buffer 
226     assign    Dq  = Dq_out; 
227  
228     // Timing Check 
229     time      MRD_chk; 
230     time      RFC_chk; 
231     time      RRD_chk; 
232     time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; 
233     time      RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3; 
234     time      RC_chk0, RC_chk1, RC_chk2, RC_chk3; 
235     time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; 
236     time      RP_chk0, RP_chk1, RP_chk2, RP_chk3; 
237     time      WR_chk0, WR_chk1, WR_chk2, WR_chk3; 
238  
239     initial begin 
240         CkeZ = 1'b0; 
241         Sys_clk = 1'b0; 
242         {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; 
243         {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111; 
244         Dqs_int = 1'b0; 
245         Dqs_out = {DQS_BITS{1'bz}}; 
246         Dq_out = {DQ_BITS{1'bz}}; 
247         Data_in_enable = 1'b0; 
248         Data_out_enable = 1'b0; 
249         DLL_enable = 1'b0; 
250         DLL_reset = 1'b0; 
251         DLL_done = 1'b0; 
252         DLL_count = 0; 
253         aref_count = 0; 
254         Prech_count = 0; 
255         power_up_done = 0; 
256         MRD_chk = 0; 
257         RFC_chk = 0; 
258         RRD_chk = 0; 
259         {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; 
260         {RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0; 
261         {RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0; 
262         {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; 
263         {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; 
264         {WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0; 
265         $timeformat (-9, 3, " ns", 12); 
266     end 
267  
268     // System Clock 
269     always begin 
270         @ (posedge Clk) begin 
271             Sys_clk = CkeZ; 
272             CkeZ = Cke; 
273         end 
274         @ (negedge Clk) begin 
275             Sys_clk = 1'b0; 
276         end