readme.txt

ddr ram controller vhdl code

1 ******************************************************************************************** 
2 The sim folder has sample test_bench files to simulate the designs in Modelsim environment.  
3 This folder has the memory model, test bench, glbl file and required parameter files.  
4 Read the steps in this file before simulations are done. 
5  
6 To run simulations for this sample configuration, user has to generate the RTL from the tool for the following GUI  
7 options. 
8  
9 Data_width                : 64 
10 HDL                       : Verilog or VHDL 
11 Memory configuration      : x16 
12 DIMM/Component            : Component  
13 Memory Part No            : MT46V16M16XX-5 
14 Add test bench            : Yes 
15 Use DCM                   : Yes 
16 Number of controllers     : 1 
17 Number of Write pipelines : 4 
18  
19 -----------------------------------------------For Verilog or VHDL---------------------------------------------------------- 
20   
21 1. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder  
22    to the project Also add the memory model, test bench and glbl files from the sim folder.  
23  
24 2. Compile the design. 
25  
26 3. After successful compilation of design load the design using the following comamnd.  
27  
28    vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl 
29    Note : User should set proper path for unisim verilog libraries 
30  
31 4. After the design is successfully loaded, run the simulations and view the waveforms.  
32  
33  
34 Notes :  
35  
36 1. To run simulations for different data widths and configurations, users should modify the test bench files 
37     with right memory models and design files. 
38  
39 2. User must manually change the frequency of the test bench for proper simulations. 
40     
41 3. Users should modify the test bench files for without test bench case. 
42     
43