ddr_include.v

ddr ram controller vhdl code

//--------------------------------------------------------------------------- 
2 // DDR Controller 
3 //  
4 // (c) Joerg Bornschein (<[e-mail]>) 
5 //--------------------------------------------------------------------------- 
6  
7 `ifdef DDR_INCLUDE_V 
8 `else 
9 `define DDR_INCLUDE_V 
10  
11 `timescale 1ns/10ps 
12  
13 //--------------------------------------------------------------------------- 
14 // Frequency  
15 //--------------------------------------------------------------------------- 
16 `define SYS_CLK_FREQUENCY   50000     // in kHz 
17 `define DDR_CLK_MULTIPLY    5         
18 `define DDR_CLK_DIVIDE      2 
19  
20 //--------------------------------------------------------------------------- 
21 // FML ranges 
22 //--------------------------------------------------------------------------- 
23 `define FML_ADR_RNG     25:4  
24 `define FML_ADR_BA_RNG  25:24 
25 `define FML_ADR_ROW_RNG 23:11 
26 `define FML_ADR_COL_RNG 10:4 
27 `define FML_DAT_RNG    127:0 
28 `define FML_MSK_RNG     15:0 
29  
30 //--------------------------------------------------------------------------- 
31 // Width 
32 //--------------------------------------------------------------------------- 
33 `define CMD_WIDTH  3 
34 `define A_WIDTH    13 
35 `define BA_WIDTH   2 
36 `define DQ_WIDTH   16 
37 `define DQS_WIDTH  2 
38 `define DM_WIDTH   2 
39  
40 `define RFIFO_WIDTH  (2 * `DQ_WIDTH ) 
41 `define WFIFO_WIDTH  (2 * (`DQ_WIDTH + `DM_WIDTH)) 
42 `define CBA_WIDTH    (`CMD_WIDTH+`BA_WIDTH+`A_WIDTH) 
43  
44 // Ranges 
45 `define CMD_RNG      (`CMD_WIDTH-1):0 
46 `define A_RNG        (`A_WIDTH-1):0 
47 `define BA_RNG       (`BA_WIDTH-1):0 
48 `define DQ_RNG       (`DQ_WIDTH-1):0 
49 `define DQS_RNG      (`DQS_WIDTH-1):0 
50 `define DM_RNG       (`DM_WIDTH-1):0 
51  
52 `define RFIFO_RNG    (`RFIFO_WIDTH-1):0 
53 `define WFIFO_RNG    (`WFIFO_WIDTH-1):0 
54 `define WFIFO_D0_RNG (1*`DQ_WIDTH-1):0 
55 `define WFIFO_D1_RNG (2*`DQ_WIDTH-1):(`DQ_WIDTH) 
56 `define WFIFO_M0_RNG (2*`DQ_WIDTH+1*`DM_WIDTH-1):(2*`DQ_WIDTH+0*`DM_WIDTH) 
57 `define WFIFO_M1_RNG (2*`DQ_WIDTH+2*`DM_WIDTH-1):(2*`DQ_WIDTH+1*`DM_WIDTH) 
58 `define CBA_RNG      (`CBA_WIDTH-1):0 
59 `define CBA_CMD_RNG  (`CBA_WIDTH-1):(`CBA_WIDTH-3) 
60 `define CBA_BA_RNG   (`CBA_WIDTH-4):(`CBA_WIDTH-5) 
61 `define CBA_A_RNG    (`CBA_WIDTH-6):0 
62  
63 `define ROW_RNG      12:0 
64  
65 //--------------------------------------------------------------------------- 
66 // DDR  
67 //--------------------------------------------------------------------------- 
68 `define DDR_CMD_NOP   3'b111 
69 `define DDR_CMD_ACT   3'b011 
70 `define DDR_CMD_READ  3'b101 
71 `define DDR_CMD_WRITE 3'b100 
72 `define DDR_CMD_TERM  3'b110 
73 `define DDR_CMD_PRE   3'b010 
74 `define DDR_CMD_AR    3'b001 
75 `define DDR_CMD_MRS   3'b000 
76  
77 `define T_MRD   2           // Mode register set  
78 `define T_RP    2           // Precharge Command Period 
79 `define T_RFC   8           // Precharge Command Period 
80  
81 `define DDR_INIT_EMRS   `A_WIDTH'b0000000000000  // DLL enable 
82 `define DDR_INIT_MRS1   `A_WIDTH'b0000101100011  // BURST=8, CL=2.5, DLL RESET 
83 `define DDR_INIT_MRS2   `A_WIDTH'b0000001100011  // BURST=8, CL=2.5 
84  
85 `define ADR_BA_RNG    25:24 
86 `define ADR_ROW_RNG   23:11 
87 `define ADR_COL_RNG   10:4 
88  
89 `endif