ddr_pulse78.v

ddr ram controller vhdl code

//---------------------------------------------------------------------------- 
2 // Wishbone DDR Controller 
3 //  
4 // (c) Joerg Bornschein (<[e-mail]>) 
5 //---------------------------------------------------------------------------- 
6 `include "ddr_include.v" 
7  
8 module ddr_pulse78 #( 
9         parameter    clk_freq = 50000000 
10 ) ( 
11         input        clk, 
12         input        reset, 
13         // 
14         output   reg pulse78 
15 ); 
16  
17 //---------------------------------------------------------------------------- 
18 // 
19 //---------------------------------------------------------------------------- 
20 `define PULSE78_RNG  10:0 
21  
22 parameter pulse78_init = 78 * (clk_freq/10000000); 
23  
24 reg [`PULSE78_RNG] counter; 
25  
26 always @(posedge clk) 
27 begin 
28         if (reset) begin 
29                 counter <= pulse78_init; 
30                 pulse78 <= 0; 
31         end else begin 
32                 if (counter == 0) begin 
33                         counter <= pulse78_init; 
34                         pulse78 <= 1'b1; 
35                 end else begin 
36                         counter <= counter - 1; 
37                         pulse78 <= 0; 
38                 end 
39         end 
40 end 
41  
42 endmodule