rotary.v

ddr ram controller vhdl code

//---------------------------------------------------------------------------- 
2 // Decode rotary encoder to clk-syncronous signals 
3 // 
4 // (c) Joerg Bornschein (<[e-mail]>) 
5 //---------------------------------------------------------------------------- 
6  
7 module rotary ( 
8         input        clk, 
9         input        reset, 
10         input [2:0]  rot, 
11         // 
12         output reg   rot_btn, 
13         output reg   rot_event, 
14         output reg   rot_left 
15 ); 
16  
17 //---------------------------------------------------------------------------- 
18 // decode rotary encoder 
19 //---------------------------------------------------------------------------- 
20 reg [1:0] rot_q; 
21  
22 always @(posedge clk) 
23 begin 
24         case (rot[1:0]) 
25                 2'b00: rot_q <= { rot_q[1], 1'b0 }; 
26                 2'b01: rot_q <= { 1'b0, rot_q[0] }; 
27                 2'b10: rot_q <= { 1'b1, rot_q[0] }; 
28                 2'b11: rot_q <= { rot_q[1], 1'b1 }; 
29         endcase 
30 end 
31  
32 reg [1:0] rot_q_delayed; 
33  
34 always @(posedge clk) 
35 begin 
36         rot_q_delayed <= rot_q; 
37  
38         if (rot_q[0] && ~rot_q_delayed[0]) begin 
39                 rot_event <= 1; 
40                 rot_left  <= rot_q[1]; 
41         end else 
42                 rot_event <= 0; 
43 end 
44  
45 //---------------------------------------------------------------------------- 
46 // debounce push button (rot[2]) 
47 //---------------------------------------------------------------------------- 
48 reg [2:0]  rot_d; 
49 reg [15:0] dead_count; 
50  
51 always @(posedge clk) 
52 begin 
53         if (reset) begin 
54                 rot_btn    <= 0; 
55                 dead_count <= 0; 
56         end else begin 
57                 rot_btn <= 1'b0; 
58                 rot_d   <= { rot_d[1:0], rot[2] }; 
59  
60                 if (dead_count == 0) begin 
61                         if ( rot_d[2:1] == 2'b01 ) begin 
62                                 rot_btn    <= 1'b1; 
63                                 dead_count <= dead_count - 1; 
64                         end 
65                 end else 
66                         dead_count <= dead_count - 1; 
67         end 
68 end 
69  
70 endmodule