gray_counter.v

ddr ram controller vhdl code

//========================================== 
2 // Function : Code Gray counter. 
3 // Coder    : Alex Claros F. 
4 // Date     : 15/May/2005. 
5 //======================================= 
6  
7 `timescale 1ns/1ps 
8  
9 module GrayCounter 
10    #(parameter   COUNTER_WIDTH = 2) 
11     
12     (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output. 
13      
14      input wire                         Enable_in,  //Count enable. 
15      input wire                         Clear_in,   //Count reset. 
16      
17      input wire                         Clk); 
18  
19     /////////Internal connections & variables/////// 
20     reg    [COUNTER_WIDTH-1:0]         BinaryCount; 
21  
22     /////////Code/////////////////////// 
23      
24     always @ (posedge Clk) 
25         if (Clear_in) begin 
26             BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;  //Gray count begins @ '1' with 
27             GrayCount_out <= {COUNTER_WIDTH{1'b 0}};      // first 'Enable_in'. 
28         end 
29         else if (Enable_in) begin 
30             BinaryCount   <= BinaryCount + 1; 
31             GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1], 
32                               BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]}; 
33         end 
34      
35 endmodule 
rr