system.ucf

ddr ram controller vhdl code

1 # ==== Clock inputs (CLK) ==== 
2  
3 NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ; 
4 NET "clk" PERIOD = 20 HIGH 50%;   # 50 MHZ 
5 # NET "clk" PERIOD = 14.28571 HIGH 50%;   # 70 MHZ 
6  
7 NET "reset"   LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; 
8  
9 # ==== Ignore timing over async-fifos ==== 
10 NET "clk_IBUFG"               TNM="SYS_CLK"; 
11 NET "*/clkgen/write_clk_u"    TNM="WRITE_CLK"; 
12 NET "*/clkgen/write_clk90_u"  TNM="WRITE_CLK"; 
13 NET "*/clkgen/read_clk_u"     TNM="READ_CLK"; 
14 #NET "*/clkgen/read_clk180_u"  TNM="DDR_CLK"; 
15  
16 TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG; 
17 TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG; 
18  
19 TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG; 
20 TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG; 
21  
22 TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG; 
23 TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG; 
24  
25 # ==== Place both DCMs at the bottom ==== 
26 #INST "*/clkgen/dcm_fx"    LOC="DCM_X0Y1"; 
27 #INST "*/clkgen/dcm_phase" LOC="DCM_X1Y1"; 
28  
29 # ==== DDR SDRAM (SD) ====   (I/O Bank 3, VCCO=2.5V) 
30 NET "ddr_clk"         LOC = "J5" | IOSTANDARD = SSTL2_I ; 
31 NET "ddr_clk_n"       LOC = "J4" | IOSTANDARD = SSTL2_I ; 
32 NET "ddr_a<0>"        LOC = "T1" | IOSTANDARD = SSTL2_I ; 
33 NET "ddr_a<1>"        LOC = "R3" | IOSTANDARD = SSTL2_I ; 
34 NET "ddr_a<2>"        LOC = "R2" | IOSTANDARD = SSTL2_I ; 
35 NET "ddr_a<3>"        LOC = "P1" | IOSTANDARD = SSTL2_I ; 
36 NET "ddr_a<4>"        LOC = "F4" | IOSTANDARD = SSTL2_I ; 
37 NET "ddr_a<5>"        LOC = "H4" | IOSTANDARD = SSTL2_I ; 
38 NET "ddr_a<6>"        LOC = "H3" | IOSTANDARD = SSTL2_I ; 
39 NET "ddr_a<7>"        LOC = "H1" | IOSTANDARD = SSTL2_I ; 
40 NET "ddr_a<8>"        LOC = "H2" | IOSTANDARD = SSTL2_I ; 
41 NET "ddr_a<9>"        LOC = "N4" | IOSTANDARD = SSTL2_I ; 
42 NET "ddr_a<10>"       LOC = "T2" | IOSTANDARD = SSTL2_I ; 
43 NET "ddr_a<11>"       LOC = "N5" | IOSTANDARD = SSTL2_I ; 
44 NET "ddr_a<12>"       LOC = "P2" | IOSTANDARD = SSTL2_I ; 
45 NET "ddr_ba<0>"       LOC = "K5" | IOSTANDARD = SSTL2_I ; 
46 NET "ddr_ba<1>"       LOC = "K6" | IOSTANDARD = SSTL2_I ; 
47 NET "ddr_dq<0>"       LOC = "L2" | IOSTANDARD = SSTL2_I ; 
48 NET "ddr_dq<1>"       LOC = "L1" | IOSTANDARD = SSTL2_I ; 
49 NET "ddr_dq<2>"       LOC = "L3" | IOSTANDARD = SSTL2_I ; 
50 NET "ddr_dq<3>"       LOC = "L4" | IOSTANDARD = SSTL2_I ; 
51 NET "ddr_dq<4>"       LOC = "M3" | IOSTANDARD = SSTL2_I ; 
52 NET "ddr_dq<5>"       LOC = "M4" | IOSTANDARD = SSTL2_I ; 
53 NET "ddr_dq<6>"       LOC = "M5" | IOSTANDARD = SSTL2_I ; 
54 NET "ddr_dq<7>"       LOC = "M6" | IOSTANDARD = SSTL2_I ; 
55 NET "ddr_dq<8>"       LOC = "E2" | IOSTANDARD = SSTL2_I ; 
56 NET "ddr_dq<9>"       LOC = "E1" | IOSTANDARD = SSTL2_I ; 
57 NET "ddr_dq<10>"      LOC = "F1" | IOSTANDARD = SSTL2_I ; 
58 NET "ddr_dq<11>"      LOC = "F2" | IOSTANDARD = SSTL2_I ; 
59 NET "ddr_dq<12>"      LOC = "G6" | IOSTANDARD = SSTL2_I ; 
60 NET "ddr_dq<13>"      LOC = "G5" | IOSTANDARD = SSTL2_I ; 
61 NET "ddr_dq<14>"      LOC = "H6" | IOSTANDARD = SSTL2_I ; 
62 NET "ddr_dq<15>"      LOC = "H5" | IOSTANDARD = SSTL2_I ; 
63 NET "ddr_dm<0>"       LOC = "J2" | IOSTANDARD = SSTL2_I ; 
64 NET "ddr_dm<1>"       LOC = "J1" | IOSTANDARD = SSTL2_I ; 
65 NET "ddr_dqs<0>"      LOC = "L6" | IOSTANDARD = SSTL2_I ; 
66 NET "ddr_dqs<1>"      LOC = "G3" | IOSTANDARD = SSTL2_I ; 
67 NET "ddr_cs_n"        LOC = "K4" | IOSTANDARD = SSTL2_I ; 
68 NET "ddr_cke"         LOC = "K3" | IOSTANDARD = SSTL2_I ; 
69 NET "ddr_ras_n"       LOC = "C1" | IOSTANDARD = SSTL2_I ; 
70 NET "ddr_cas_n"       LOC = "C2" | IOSTANDARD = SSTL2_I ; 
71 NET "ddr_we_n"        LOC = "D1" | IOSTANDARD = SSTL2_I ; 
72  
73 # Path to allow connection to top DCM connection 
74 #NET "ddr_clk_fb"      LOC = "B9" | IOSTANDARD = LVCMOS33 ; 
75  
76 # ==== UART ==== 
77 NET "uart_rxd" LOC = "R7"  | IOSTANDARD = LVTTL ; 
78 NET "uart_txd" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; 
79  
80 # ==== LED output === 
81 NET "led<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
82 NET "led<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
83 NET "led<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
84 NET "led<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
85 NET "led<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
86 NET "led<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
87 NET "led<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
88 NET "led<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; 
89  
90 # ==== rotary encoder ==== 
91 NET "rot<0>"  LOC = "K18" | IOSTANDARD = LVTTL | PULLUP   ; 
92 NET "rot<1>"  LOC = "G18" | IOSTANDARD = LVTTL | PULLUP   ; 
93 NET "rot<2>"  LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;