system.xst

ddr ram controller vhdl code

1 run 
2 -ifn system.prj 
3 -top system 
4 -ifmt MIXED 
5 -opt_mode AREA 
6 -opt_level 2 
7 -register_balancing yes 
8 -ofn system.ngc 
9 -p  xc3s500e-fg320-4 
10 #-p  xc2vp30-7fg676 
11