fml_memtest.v

ddr ram controller vhdl code

//---------------------------------------------------------------------------- 
2 // FML (FastMemoryLink) Memory Test Component 
3 //  
4 // (c) Joerg Bornschein (<[e-mail]>) 
5 //---------------------------------------------------------------------------- 
6 `include "ddr_include.v" 
7  
8 module fml_memtest  
9 ( 
10         input                        clk, 
11         input                        reset, 
12         output  [7:0]                led, 
13         //  
14         output reg                   fml_rd, 
15         output reg                   fml_wr, 
16         input                        fml_done, 
17         output reg  [`FML_ADR_RNG]   fml_adr, 
18         output reg  [`FML_DAT_RNG]   fml_wdata, 
19         output reg  [`FML_MSK_RNG]   fml_msk, 
20         input       [`FML_DAT_RNG]   fml_rdata 
21 ); 
22  
23  
24 //---------------------------------------------------------------------------- 
25 // StartUp wait 
26 //---------------------------------------------------------------------------- 
27 reg [10:0]  su_counter; 
28 wire       su_wait; 
29 assign     su_wait = ~(su_counter == 600); 
30  
31 always @(posedge clk) 
32 begin 
33         if (reset) 
34                 su_counter <= 0; 
35         else if (su_wait) 
36                 su_counter <= su_counter + 1; 
37 end 
38  
39 //---------------------------------------------------------------------------- 
40 // FML Memory Test  
41 //---------------------------------------------------------------------------- 
42 reg [30:0] r_instr; 
43 reg [30:0] w_instr; 
44  
45 reg [4:0] r_counter;  
46 reg [4:0] w_counter;  
47  
48 wire [`FML_ADR_RNG] r_adr; 
49 wire [`FML_ADR_RNG] w_adr; 
50  
51 assign r_adr = { 1'b0, r_counter[4], 11'b0, r_counter[3:2], 5'b0, r_counter[1:0] }; 
52 assign w_adr = { 1'b0, w_counter[4], 11'b0, w_counter[3:2], 5'b0, w_counter[1:0] }; 
53  
54 wire [127:0] c_data = 'hFFEEDDCCBBAA99887766554433221100; 
55 wire [127:0] r_data = c_data ^ { r_adr, r_adr, r_adr, r_adr, r_adr, 18'b0 }; 
56 wire [127:0] w_data = c_data ^ { w_adr, w_adr, w_adr, w_adr, w_adr, 18'b0 }; 
57  
58 reg  [127:0] comp_data; 
59  
60 reg    wait_done; 
61 assign stall = (wait_done & ~fml_done); 
62  
63 always @(posedge clk) 
64 begin 
65         if (reset) begin 
66 //              r_instr     <= 'b001010101100110011110000; 
67 //              w_instr     <= 'b000101010011001100001111; 
68                 r_instr     <= 'b0101010101011001100110011110000; 
69                 w_instr     <= 'b0010101010100110011001100001111; 
70                 fml_msk     <= 'h0000; 
71                 wait_done   <= 0; 
72                 fml_rd      <= 0; 
73                 fml_wr      <= 0; 
74                 r_counter   <= 1; 
75                 w_counter   <= 1; 
76         end else begin 
77                 if (~stall & ~su_wait) begin 
78                         if (r_instr[0]) begin            // READ 
79                                 fml_rd    <= 1; 
80                                 fml_wr    <= 0; 
81                                 fml_adr   <= r_adr; 
82                                 comp_data <= r_data; 
83                                 r_counter <= r_counter + 1; 
84                                 wait_done <= 1; 
85                         end else if (w_instr[0]) begin   // WRITE 
86                                 fml_rd    <= 0; 
87                                 fml_wr    <= 1; 
88                                 fml_wdata <= w_data; 
89                                 fml_adr   <= w_adr; 
90                                 w_counter <= w_counter + 1; 
91                                 wait_done <= 1; 
92                         end else begin                   // IDLE CYCLE 
93                                 fml_rd    <= 0; 
94                                 fml_wr    <= 0; 
95                                 fml_adr   <= 'b0; 
96                                 wait_done <= 0; 
97                         end 
98  
99                         r_instr <= { r_instr[0], r_instr[23:1] }; 
100                         w_instr <= { w_instr[0], w_instr[23:1] }; 
101                 end 
102         end 
103 end 
104  
105 reg data_ok; 
106 reg data_ok_lt; 
107 reg data_error; 
108 reg data_error_lt; 
109  
110 always @(posedge clk) 
111 begin 
112         if (reset) begin 
113                 data_ok         <= 0; 
114                 data_ok_lt      <= 0; 
115                 data_error      <= 0; 
116                 data_error_lt   <= 0; 
117         end else begin 
118                 if (fml_rd & fml_done) begin 
119                         if (fml_rdata == comp_data) begin 
120                                 data_ok       <= 1; 
121                                 data_ok_lt    <= 1; 
122                                 data_error    <= 0; 
123                         end else begin 
124                                 data_error    <= 1; 
125                                 data_error_lt <= 1; 
126                                 data_ok       <= 0; 
127                         end 
128                 end 
129         end 
130 end 
131  
132  
133 //---------------------------------------------------------------------------- 
134 // LED - Status output 
135 //---------------------------------------------------------------------------- 
136  
137 assign led[7] = fml_rd; 
138 assign led[6] = fml_wr; 
139 assign led[5] = fml_done; 
140 assign led[4] = 0; 
141 assign led[3] = data_ok; 
142 assign led[2] = data_ok_lt; 
143 assign led[1] = data_error; 
144 assign led[0] = data_error_lt; 
145  
146 endmodule