system.v

ddr ram controller vhdl code

//---------------------------------------------------------------------------- 
2 // DDR Controller Test Design 
3 //  
4 // (c) Joerg Bornschein (<[e-mail]>) 
5 //---------------------------------------------------------------------------- 
6 `timescale 1ns / 1ps 
7 `include "ddr_include.v" 
8  
9 module system 
10 #( 
11         parameter clk_freq         = 50000000, 
12         parameter ddr_clk_multiply = 12, 
13         parameter ddr_clk_divide   = 5, 
14         parameter ddr_phase_shift  = 20, 
15         parameter ddr_wait200_init = 26 
16 ) 
17 ( 
18         input                   clk, 
19         input                   reset, 
20         // DDR connection 
21         output                  ddr_clk, 
22         output                  ddr_clk_n, 
23         input                   ddr_clk_fb, 
24         output                  ddr_ras_n, 
25         output                  ddr_cas_n, 
26         output                  ddr_we_n, 
27         output                  ddr_cke, 
28         output                  ddr_cs_n, 
29         output [  `A_RNG]       ddr_a, 
30         output [ `BA_RNG]       ddr_ba, 
31         inout  [ `DQ_RNG]       ddr_dq, 
32         inout  [`DQS_RNG]       ddr_dqs, 
33         output [ `DM_RNG]       ddr_dm, 
34         // LAC (LogicAnalyzerComponent) 
35         input                   uart_rxd, 
36         output                  uart_txd, 
37         // diagnosis 
38         output [7:0]            led, 
39         input  [2:0]            rot 
40 ); 
41  
42 //---------------------------------------------------------------------------- 
43 // Memory-Tester  
44 //---------------------------------------------------------------------------- 
45 wire                fml_rd; 
46 wire                fml_wr; 
47 wire                fml_done; 
48 wire [`FML_ADR_RNG] fml_adr; 
49 wire [`FML_DAT_RNG] fml_wdata; 
50 wire [`FML_MSK_RNG] fml_msk; 
51 wire [`FML_DAT_RNG] fml_rdata; 
52  
53 fml_memtest test0 ( 
54         .clk(          clk         ), 
55         .reset(        reset       ), 
56         .led(          led         ), 
57         // FML 
58         .fml_wr(       fml_wr      ), 
59         .fml_rd(       fml_rd      ), 
60         .fml_done(     fml_done    ), 
61         .fml_adr(      fml_adr     ), 
62         .fml_wdata(    fml_wdata   ), 
63         .fml_msk(      fml_msk     ), 
64         .fml_rdata(    fml_rdata   ) 
65 ); 
66  
67 //---------------------------------------------------------------------------- 
68 // DDR Controller 
69 //---------------------------------------------------------------------------- 
70 ddr_ctrl #( 
71         .clk_freq(     clk_freq         ), 
72         .clk_multiply( ddr_clk_multiply ), 
73         .clk_divide(   ddr_clk_divide   ), 
74         .phase_shift(  ddr_phase_shift  ), 
75         .wait200_init( ddr_wait200_init ) 
76 ) ctrl0 ( 
77         .clk(     clk    ), 
78         .reset(   reset  ), 
79         // DDR Ports 
80         .ddr_clk(      ddr_clk     ), 
81         .ddr_clk_n(    ddr_clk_n   ), 
82         .ddr_clk_fb(   ddr_clk_fb  ), 
83         .ddr_ras_n(    ddr_ras_n   ), 
84         .ddr_cas_n(    ddr_cas_n   ), 
85         .ddr_we_n(     ddr_we_n    ), 
86         .ddr_cke(      ddr_cke     ), 
87         .ddr_cs_n(     ddr_cs_n    ), 
88         .ddr_a(        ddr_a       ), 
89         .ddr_ba(       ddr_ba      ), 
90         .ddr_dq(       ddr_dq      ), 
91         .ddr_dqs(      ddr_dqs     ), 
92         .ddr_dm(       ddr_dm      ), 
93         // FML (FastMemoryLink) 
94         .fml_wr(       fml_wr      ), 
95         .fml_rd(       fml_rd      ), 
96         .fml_done(     fml_done    ), 
97         .fml_adr(      fml_adr     ), 
98         .fml_din(      fml_wdata   ), 
99         .fml_msk(      fml_msk     ), 
100         .fml_dout(     fml_rdata   ), 
101         // phase shifting 
102         .rot(          rot         ) 
103 ); 
104  
105 //---------------------------------------------------------------------------- 
106 // DDR Controller 
107 //---------------------------------------------------------------------------- 
108 wire [7:0] probe; 
109 wire [7:0] probe_sel; 
110  
111 assign probe = { fml_rd, fml_wr, fml_done, 5'b0 }; 
112  
113  
114 lac #( 
115         .uart_freq_hz( clk_freq ), 
116         .uart_baud(    115200   ), 
117         .adr_width(    13       ) 
118 ) lac0 ( 
119         .reset(      reset    ), 
120         .uart_clk(   clk      ), 
121         .uart_rxd(   uart_rxd ), 
122         .uart_cts(), 
123         .uart_txd(   uart_txd ), 
124         .uart_rts(   1'b1     ), 
125         // 
126         .probe_clk(  clk      ), 
127         .probe(      probe    ), 
128         .select(     probe_sel) 
129 ); 
130  
131 endmodule 
132  
133 // vim: set ts=4