📄 cpld_dsp.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------- LC118 EA5
| +----------- LC125 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node3
| | +--------- LC121 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node3
| | | +------- LC123 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node3
| | | | +----- LC114 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node4
| | | | | +--- LC116 ~968~1
| | | | | | +- LC113 ~968~2
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'H'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC118-> * - - - - * * | * - * * * * * * | <-- EA5
LC116-> * - - - - - - | - - - - - - - * | <-- ~968~1
LC113-> * - - - - - - | - - - - - - - * | <-- ~968~2
Pin
58 -> * - - - - * * | * - * * * * * * | <-- ad_num0
57 -> * - - - - * * | * - * * * * * * | <-- ad_num1
30 -> * - - - - * * | * - * * * * * * | <-- AD1_BUSY
77 -> * - - - - * * | * - * * * * * * | <-- delaytime1
81 -> - - - - - * * | * - * * - * - * | <-- dp_num
16 -> * * * * * - - | * - * * * * * * | <-- EA0
18 -> * * * * * - - | * - * * * * * * | <-- EA1
19 -> * * * * * - - | * - * * * * * * | <-- EA2
83 -> * - - - - * - | * - * * - * * * | <-- EA6
85 -> * - - - - - - | * - * * * * * * | <-- EA7
86 -> * - - - - * - | * - * * - * * * | <-- EA8
87 -> * - - - - - - | * - * * * * * * | <-- EA9
94 -> * - - - - * - | * - * * - * * * | <-- EA10
89 -> - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - - | * - * * * * * * | <-- wr_en1
LC81 -> - * * * * * - | * - * * * * * * | <-- EA3
LC105-> * - - - * * - | * - * * * * * * | <-- EA4
LC73 -> * - - - - - - | * - * * * * * * | <-- EA11
LC69 -> * - - - - - - | * - * * * * * * | <-- EA12
LC95 -> * - - - - * * | - - - - - - - * | <-- |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node5
LC94 -> - - - - - * * | - - - - - - - * | <-- |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node5
LC92 -> * - - - - - * | - - - - - - - * | <-- |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node5
LC90 -> * - - - - * * | - - - - - - - * | <-- |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node5
LC87 -> - - - - - * * | - - - - - - - * | <-- |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node5
LC84 -> * - - - - * * | - - - - - - - * | <-- |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** EQUATIONS **
ad_num0 : INPUT;
ad_num1 : INPUT;
AD0 : INPUT;
AD1_BUSY : INPUT;
AD1 : INPUT;
AD2_BUSY : INPUT;
AD2 : INPUT;
AD3_BUSY : INPUT;
AD3 : INPUT;
AD4 : INPUT;
AD5 : INPUT;
AD6 : INPUT;
AD7 : INPUT;
AD8 : INPUT;
AD9 : INPUT;
AD10 : INPUT;
AD11 : INPUT;
delaytime1 : INPUT;
dp_num : INPUT;
EA0 : INPUT;
EA1 : INPUT;
EA2 : INPUT;
EA6 : INPUT;
EA7 : INPUT;
EA8 : INPUT;
EA9 : INPUT;
EA10 : INPUT;
EA11 : INPUT;
EA12 : INPUT;
GCLK1 : INPUT;
GCLK2 : INPUT;
KEY0 : INPUT;
KEY1 : INPUT;
KEY2 : INPUT;
KEY3 : INPUT;
KEY4 : INPUT;
wr_en1 : INPUT;
-- Node name is 'AD1_RD' = 'ad1_ctl'
-- Equation name is 'AD1_RD', location is LC064, type is output.
AD1_RD = DFFE( _EQ001 $ _EQ002, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ001 = !ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA0 & !EA1 & EA2 &
!EA3 & EA4 & !EA5 & EA6 & !EA7 & EA8 & !EA9 & EA10 & !_LC069 &
!_LC073 & !_LC097 & !_LC098 & !_LC103 & _X001
# !ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA2 & !EA3 & EA4 &
!EA5 & EA6 & !EA7 & EA8 & !EA9 & EA10 & !_LC069 & !_LC073 &
!_LC097 & !_LC098 & !_LC103 & _X001
# !ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA4 & !EA5 & EA6 &
!EA7 & EA8 & !EA9 & EA10 & !_LC069 & !_LC073 & !_LC097 &
!_LC098 & !_LC103 & _X001;
_X001 = EXP( AD1_BUSY & !AD1_RD);
_EQ002 = !_LC097 & !_LC098 & !_LC103 & _X001;
_X001 = EXP( AD1_BUSY & !AD1_RD);
-- Node name is 'AD2_RD' = 'ad2_ctl'
-- Equation name is 'AD2_RD', location is LC035, type is output.
AD2_RD = DFFE( _EQ003 $ _EQ004, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ003 = ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA0 & !EA1 & !EA3 &
!EA5 & !EA7 & !EA9 & !_LC045 & !_LC046 & !_LC069 & !_LC073 &
_X002 & _X003 & _X004 & _X005 & _X006
# ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA2 & !EA3 & !EA5 &
!EA7 & !EA9 & !_LC045 & !_LC046 & !_LC069 & !_LC073 & _X002 &
_X003 & _X004 & _X005 & _X006
# ad_num0 & !ad_num1 & !AD1_BUSY & !delaytime1 & !EA4 & !EA5 & !EA7 &
!EA9 & !_LC045 & !_LC046 & !_LC069 & !_LC073 & _X002 & _X003 &
_X004 & _X005 & _X006;
_X002 = EXP(!ad_num0 & !AD2_RD & delaytime1);
_X003 = EXP( ad_num0 & !AD2_RD & !delaytime1);
_X004 = EXP(!AD2_RD & _LC073);
_X005 = EXP(!AD2_RD & _LC069);
_X006 = EXP( AD1_BUSY & !AD2_RD);
_EQ004 = !_LC045 & !_LC046 & _X002 & _X003 & _X004 & _X005 & _X006;
_X002 = EXP(!ad_num0 & !AD2_RD & delaytime1);
_X003 = EXP( ad_num0 & !AD2_RD & !delaytime1);
_X004 = EXP(!AD2_RD & _LC073);
_X005 = EXP(!AD2_RD & _LC069);
_X006 = EXP( AD1_BUSY & !AD2_RD);
-- Node name is 'AD3_RD' = 'ad3_ctl'
-- Equation name is 'AD3_RD', location is LC072, type is output.
AD3_RD = DFFE( _EQ005 $ _EQ006, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ005 = !ad_num0 & ad_num1 & !AD1_BUSY & !delaytime1 & !EA0 & !EA1 & !EA3 &
!EA5 & !EA7 & !EA9 & !_LC034 & !_LC047 & !_LC069 & !_LC073 &
_X007 & _X008 & _X009 & _X010 & _X011
# !ad_num0 & ad_num1 & !AD1_BUSY & !delaytime1 & !EA2 & !EA3 & !EA5 &
!EA7 & !EA9 & !_LC034 & !_LC047 & !_LC069 & !_LC073 & _X007 &
_X008 & _X009 & _X010 & _X011
# !ad_num0 & ad_num1 & !AD1_BUSY & !delaytime1 & !EA4 & !EA5 & !EA7 &
!EA9 & !_LC034 & !_LC047 & !_LC069 & !_LC073 & _X007 & _X008 &
_X009 & _X010 & _X011;
_X007 = EXP(!ad_num1 & !AD3_RD & delaytime1);
_X008 = EXP( ad_num1 & !AD3_RD & !delaytime1);
_X009 = EXP(!AD3_RD & _LC073);
_X010 = EXP(!AD3_RD & _LC069);
_X011 = EXP( AD1_BUSY & !AD3_RD);
_EQ006 = !_LC034 & !_LC047 & _X007 & _X008 & _X009 & _X010 & _X011;
_X007 = EXP(!ad_num1 & !AD3_RD & delaytime1);
_X008 = EXP( ad_num1 & !AD3_RD & !delaytime1);
_X009 = EXP(!AD3_RD & _LC073);
_X010 = EXP(!AD3_RD & _LC069);
_X011 = EXP( AD1_BUSY & !AD3_RD);
-- Node name is 'CE1' = 'dp_ctl0'
-- Equation name is 'CE1', location is LC011, type is output.
CE1 = DFFE( _EQ007 $ _EQ008, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ007 = !ad_num0 & !AD1_BUSY & !delaytime1 & !dp_num & !EA0 & !EA1 & EA2 &
!EA3 & EA4 & !EA5 & EA6 & !EA7 & EA8 & !EA9 & EA10 & !_LC069 &
!_LC073 & !_LC089 & !_LC091 & !_LC093 & _X012 & _X013 & _X014 &
_X015 & _X016
# !ad_num1 & !AD1_BUSY & !delaytime1 & !dp_num & !EA0 & !EA1 & EA2 &
!EA3 & EA4 & !EA5 & EA6 & !EA7 & EA8 & !EA9 & EA10 & !_LC069 &
!_LC073 & !_LC089 & !_LC091 & !_LC093 & _X012 & _X013 & _X014 &
_X015 & _X016
# !ad_num0 & !AD1_BUSY & !delaytime1 & !dp_num & !EA2 & !EA3 & EA4 &
!EA5 & EA6 & !EA7 & EA8 & !EA9 & EA10 & !_LC069 & !_LC073 &
!_LC089 & !_LC091 & !_LC093 & _X012 & _X013 & _X014 & _X015 &
_X016;
_X012 = EXP(!CE1 & !dp_num & EA9 & EA10);
_X013 = EXP(!CE1 & !dp_num & _LC073);
_X014 = EXP(!CE1 & !dp_num & _LC069);
_X015 = EXP(!CE1 & !delaytime1 & !dp_num);
_X016 = EXP( AD1_BUSY & !CE1);
_EQ008 = !_LC089 & !_LC091 & !_LC093 & _X012 & _X013 & _X014 & _X015 &
_X016;
_X012 = EXP(!CE1 & !dp_num & EA9 & EA10);
_X013 = EXP(!CE1 & !dp_num & _LC073);
_X014 = EXP(!CE1 & !dp_num & _LC069);
_X015 = EXP(!CE1 & !delaytime1 & !dp_num);
_X016 = EXP( AD1_BUSY & !CE1);
-- Node name is 'CE2' = 'dp_ctl1'
-- Equation name is 'CE2', location is LC040, type is output.
CE2 = DFFE( _EQ009 $ _EQ010, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ009 = !CE2 & dp_num & EA0 & EA2 & EA4 & EA6 & EA8 & EA10 &
!_LC036 & _X017 & _X018 & _X019
# !CE2 & dp_num & EA1 & EA2 & EA4 & EA6 & EA8 & EA10 &
!_LC036 & _X017 & _X018 & _X019
# !CE2 & dp_num & EA3 & EA4 & EA6 & EA8 & EA10 & !_LC036 &
_X017 & _X018 & _X019;
_X017 = EXP(!CE2 & dp_num & _LC069);
_X018 = EXP(!CE2 & !delaytime1 & dp_num);
_X019 = EXP( AD1_BUSY & !CE2);
_EQ010 = !_LC036 & _X017 & _X018 & _X019;
_X017 = EXP(!CE2 & dp_num & _LC069);
_X018 = EXP(!CE2 & !delaytime1 & dp_num);
_X019 = EXP( AD1_BUSY & !CE2);
-- Node name is 'CONV' = 'CNV'
-- Equation name is 'CONV', location is LC075, type is output.
CONV = DFFE( _EQ011 $ GND, GLOBAL( GCLK2), VCC, VCC, VCC);
_EQ011 = !num_add1 & !num_add2 & !num_add3 & num_add4 & num_add5 &
!num_add6 & !num_add7
# !num_add4 & num_add5 & !num_add6 & !num_add7
# !num_add5 & !num_add6 & !num_add7;
-- Node name is 'EA3' = 'stor_num3'
-- Equation name is 'EA3', location is LC081, type is output.
EA3 = DFFE( _EQ012 $ _EQ013, GLOBAL(!GCLK1), VCC, VCC, !wr_en1);
_EQ012 = EA0 & EA2 & !EA3 & EA4 & EA6 & EA8 & EA10 & !_LC082 &
!_LC088 & _X020 & _X021 & _X022 & _X023 & _X024 & _X025 &
_X026 & _X027
# EA1 & EA2 & !EA3 & EA4 & EA6 & EA8 & EA10 & !_LC082 &
!_LC088 & _X020 & _X021 & _X022 & _X023 & _X024 & _X025 &
_X026 & _X027
# !ad_num0 & !AD1_BUSY & delaytime1 & !_LC057 & !_LC061 & !_LC082 &
!_LC088 & !_LC123 & !_LC125 & _X020 & _X021 & _X022 & _X023 &
_X024 & _X025 & _X026 & _X027;
_X020 = EXP(!AD1_BUSY & _LC069);
_X021 = EXP( AD1_BUSY & !EA3);
_X022 = EXP(!AD1_BUSY & _LC073);
_X023 = EXP(!AD1_BUSY & EA3 & EA4 & EA6 & EA8 & EA10);
_X024 = EXP(!AD1_BUSY & EA5 & EA6 & EA8 & EA10);
_X025 = EXP(!AD1_BUSY & EA7 & EA8 & EA10);
_X026 = EXP(!AD1_BUSY & EA9 & EA10);
_X027 = EXP(!delaytime1 & !EA3);
_EQ013 = !_LC082 & !_LC088 & _X020 & _X021 & _X022 & _X023 & _X024 &
_X025 & _X026 & _X027;
_X020 = EXP(!AD1_BUSY & _LC069);
_X021 = EXP( AD1_BUSY & !EA3);
_X022 = EXP(!AD1_BUSY & _LC073);
_X023 = EXP(!AD1_BUSY & EA3 & EA4 & EA6 & EA8 & EA10);
_X024 = EXP(!AD1_BUSY & EA5 & EA6 & EA8 & EA10);
_X025 = EXP(!AD1_BUSY & EA7 & EA8 & EA10);
_X026 = EXP(!AD1_BUSY & EA9 & EA10);
_X027 = EXP(!delaytime1 &⌨️ 快捷键说明
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