📄 cpld_dsp.rpt
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- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------- LC64 AD1_RD
| +--------------- LC61 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node3
| | +------------- LC63 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node4
| | | +----------- LC60 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node3
| | | | +--------- LC58 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node4
| | | | | +------- LC57 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node3
| | | | | | +----- LC62 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node4
| | | | | | | +--- LC59 ~969~1
| | | | | | | | +- LC55 ~969~2
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC64 -> * - - - - - - - - | - - - * - - * - | <-- AD1_RD
LC63 -> - - - - - - - * * | - - - * - - * - | <-- |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node4
LC58 -> - - - - - - - * * | - - - * - - - - | <-- |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node4
LC62 -> - - - - - - - * * | - - - * - - * - | <-- |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node4
Pin
58 -> * - - - - - - * * | * - * * * * * * | <-- ad_num0
57 -> * - - - - - - * * | * - * * * * * * | <-- ad_num1
30 -> * - - - - - - * * | * - * * * * * * | <-- AD1_BUSY
77 -> * - - - - - - * * | * - * * * * * * | <-- delaytime1
81 -> - - - - - - - * * | * - * * - * - * | <-- dp_num
16 -> * * * * * * * - - | * - * * * * * * | <-- EA0
18 -> * * * * * * * - - | * - * * * * * * | <-- EA1
19 -> * * * * * * * - - | * - * * * * * * | <-- EA2
83 -> * - - - - - - - - | * - * * - * * * | <-- EA6
85 -> * - - - - - - - - | * - * * * * * * | <-- EA7
86 -> * - - - - - - - - | * - * * - * * * | <-- EA8
87 -> * - - - - - - - - | * - * * * * * * | <-- EA9
94 -> * - - - - - - - - | * - * * - * * * | <-- EA10
89 -> - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - - - - | * - * * * * * * | <-- wr_en1
LC81 -> * * * * * * * - - | * - * * * * * * | <-- EA3
LC105-> * - * - * - * - * | * - * * * * * * | <-- EA4
LC118-> * - - - - - - - - | * - * * * * * * | <-- EA5
LC73 -> * - - - - - - - - | * - * * * * * * | <-- EA11
LC69 -> * - - - - - - - - | * - * * * * * * | <-- EA12
LC83 -> - - - - - - - * * | - - - * - - * - | <-- |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node4
LC96 -> - - - - - - - * * | - - - * - - - - | <-- |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node4
LC114-> - - - - - - - * * | - - - * - - * - | <-- |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node4
LC97 -> * - - - - - - - - | - - - * - - - - | <-- ~1198~1
LC98 -> * - - - - - - - - | - - - * - - - - | <-- ~1198~2
LC103-> * - - - - - - - - | - - - * - - - - | <-- ~1198~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------- LC72 AD3_RD
| +----------------------- LC75 CONV
| | +--------------------- LC73 EA11
| | | +------------------- LC69 EA12
| | | | +----------------- LC66 |lpm_add_sub:1461|addcore:adder|result_node3
| | | | | +--------------- LC70 |lpm_add_sub:1461|addcore:adder|result_node7
| | | | | | +------------- LC65 |lpm_add_sub:1462|addcore:adder|result_node6
| | | | | | | +----------- LC68 |lpm_add_sub:1462|addcore:adder|result_node7
| | | | | | | | +--------- LC78 num_add5
| | | | | | | | | +------- LC71 num_add4
| | | | | | | | | | +----- LC74 num_add2
| | | | | | | | | | | +--- LC76 num_add1
| | | | | | | | | | | | +- LC77 num_add0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
LC72 -> * - - - - - - - - - - - - | - - * - * - - - | <-- AD3_RD
LC73 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA11
LC69 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA12
LC78 -> - * - - - * * * * * * - * | - * - - * - * - | <-- num_add5
LC71 -> - * - - - * * * * * * - * | - * - - * - * - | <-- num_add4
LC74 -> - * - - * * * * * * * - * | - * - - * - * - | <-- num_add2
LC76 -> - * - - * * * * * * * * * | - * - - * - * - | <-- num_add1
LC77 -> - - - - * * * * * * * * * | - * - - * - * - | <-- num_add0
Pin
58 -> * - - - - - - - - - - - - | * - * * * * * * | <-- ad_num0
57 -> * - - - - - - - - - - - - | * - * * * * * * | <-- ad_num1
30 -> * - - - - - - - - - - - - | * - * * * * * * | <-- AD1_BUSY
77 -> * - - - - - - - - - - - - | * - * * * * * * | <-- delaytime1
16 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA0
18 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA1
19 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA2
85 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA7
87 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA9
95 -> - - * - - - - - - - - - - | - - - - * - - - | <-- EA11
96 -> - - - * - - - - - - - - - | - - - - * - - - | <-- EA12
89 -> - - - - - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - - - - - - - - | * - * * * * * * | <-- wr_en1
LC81 -> * - - - - - - - - - - - - | * - * * * * * * | <-- EA3
LC105-> * - - - - - - - - - - - - | * - * * * * * * | <-- EA4
LC118-> * - - - - - - - - - - - - | * - * * * * * * | <-- EA5
LC109-> - - - - - - - - - * - - - | - - - - * - - - | <-- |lpm_add_sub:1461|addcore:adder|result_node4
LC111-> - - - - - - - - * - - - - | - - - - * - - - | <-- |lpm_add_sub:1461|addcore:adder|result_node5
LC101-> - - - - - - - - - * - - - | - - - - * - - - | <-- |lpm_add_sub:1462|addcore:adder|result_node4
LC112-> - - - - - - - - * - - - - | - - - - * - - - | <-- |lpm_add_sub:1462|addcore:adder|result_node5
LC32 -> - * - - - * - * * * * - * | - * - - * - - - | <-- num_add7
LC17 -> - * - - - * * * * * * - * | - * - - * - * - | <-- num_add6
LC28 -> - * - - * * * * * * * - * | - * - - * - * - | <-- num_add3
LC47 -> * - - - - - - - - - - - - | - - - - * - - - | <-- ~1429~1
LC34 -> * - - - - - - - - - - - - | - - - - * - - - | <-- ~1429~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------------------- LC81 EA3
| +------------------------- LC83 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node4
| | +----------------------- LC95 |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node5
| | | +--------------------- LC96 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node4
| | | | +------------------- LC94 |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node5
| | | | | +----------------- LC92 |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node5
| | | | | | +--------------- LC90 |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node5
| | | | | | | +------------- LC87 |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node5
| | | | | | | | +----------- LC84 |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | +--------- LC82 ~970~1
| | | | | | | | | | +------- LC88 ~970~2
| | | | | | | | | | | +----- LC89 ~1134~1
| | | | | | | | | | | | +--- LC91 ~1134~2
| | | | | | | | | | | | | +- LC93 ~1134~3
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC81 -> * * * * * * * * * - * * * - | * - * * * * * * | <-- EA3
LC82 -> * - - - - - - - - - - - - - | - - - - - * - - | <-- ~970~1
LC88 -> * - - - - - - - - - - - - - | - - - - - * - - | <-- ~970~2
Pin
58 -> * - - - - - - - - * * * * * | * - * * * * * * | <-- ad_num0
57 -> - - - - - - - - - * * * * * | * - * * * * * * | <-- ad_num1
30 -> * - - - - - - - - * * * * * | * - * * * * * * | <-- AD1_BUSY
77 -> * - - - - - - - - * * * * * | * - * * * * * * | <-- delaytime1
81 -> - - - - - - - - - * * * * * | * - * * - * - * | <-- dp_num
16 -> * * * * * * * * * - - - * - | * - * * * * * * | <-- EA0
18 -> * * * * * * * * * - - - * - | * - * * * * * * | <-- EA1
19 -> * * * * * * * * * - - * * - | * - * * * * * * | <-- EA2
83 -> * - - - - - - - - - - * * * | * - * * - * * * | <-- EA6
85 -> * - - - - - - - - - - * - * | * - * * * * * * | <-- EA7
86 -> * - - - - - - - - - - * * * | * - * * - * * * | <-- EA8
87 -> * - - - - - - - - - - * * - | * - * * * * * * | <-- EA9
94 -> * - - - - - - - - - - * * * | * - * * - * * * | <-- EA10
89 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - - - - - - - - - | * - * * * * * * | <-- wr_en1
LC11 -> - - - - - - - - - - - - * * | * - - - - * - - | <-- CE1
LC105-> * * * * * * * * * - - * * - | * - * * * * * * | <-- EA4
LC118-> * - * - * * * * * - - * - * | * - * * * * * * | <-- EA5
LC73 -> * - - - - - - - - - - * * * | * - * * * * * * | <-- EA11
LC69 -> * - - - - - - - - - - * * * | * - * * * * * * | <-- EA12
LC125-> * - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node3
LC121-> - - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1456|addcore:adder|addcore:adder0|result_node3
LC123-> * - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node3
LC61 -> * - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node3
LC60 -> - - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1459|addcore:adder|addcore:adder0|result_node3
LC57 -> * - - - - - - - - * * - - - | - - - - - * - - | <-- |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt
cpld_dsp
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------------------- LC105 EA4
| +--------------------- LC110 LED0
| | +------------------- LC104 LED1
| | | +----------------- LC109 |lpm_add_sub:1461|addcore:adder|result_node4
| | | | +--------------- LC111 |lpm_add_sub:1461|addcore:adder|result_node5
| | | | | +------------- LC102 |lpm_add_sub:1461|addcore:adder|result_node6
| | | | | | +----------- LC100 |lpm_add_sub:1462|addcore:adder|result_node3
| | | | | | | +--------- LC101 |lpm_add_sub:1462|addcore:adder|result_node4
| | | | | | | | +------- LC112 |lpm_add_sub:1462|addcore:adder|result_node5
| | | | | | | | | +----- LC97 ~1198~1
| | | | | | | | | | +--- LC98 ~1198~2
| | | | | | | | | | | +- LC103 ~1198~3
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC105-> * - - - - - - - - * * - | * - * * * * * * | <-- EA4
Pin
58 -> * - - - - - - - - * * * | * - * * * * * * | <-- ad_num0
57 -> - - - - - - - - - * * * | * - * * * * * * | <-- ad_num1
30 -> * - - - - - - - - * - - | * - * * * * * * | <-- AD1_BUSY
77 -> * - - - - - - - - * * * | * - * * * * * * | <-- delaytime1
16 -> * - - - - - - - - * - - | * - * * * * * * | <-- EA0
18 -> * - - - - - - - - * - - | * - * * * * * * | <-- EA1
19 -> * - - - - - - - - * - - | * - * * * * * * | <-- EA2
83 -> * - - - - - - - - * * - | * - * * - * * * | <-- EA6
85 -> * - - - - - - - - * * - | * - * * * * * * | <-- EA7
86 -> * - - - - - - - - * * - | * - * * - * * * | <-- EA8
87 -> * - - - - - - - - * - * | * - * * * * * * | <-- EA9
94 -> * - - - - - - - - * * * | * - * * - * * * | <-- EA10
89 -> - - - - - - - - - - - - | - - - - - - - - | <-- GCLK1
92 -> - - - - - - - - - - - - | - - - - - - - - | <-- GCLK2
21 -> * - - - - - - - - - - - | * - * * * * * * | <-- wr_en1
LC64 -> - - - - - - - - - * * * | - - - * - - * - | <-- AD1_RD
LC81 -> * - - - - - - - - - * - | * - * * * * * * | <-- EA3
LC118-> * - - - - - - - - - * - | * - * * * * * * | <-- EA5
LC73 -> * - - - - - - - - * - * | * - * * * * * * | <-- EA11
LC69 -> * - - - - - - - - * - * | * - * * * * * * | <-- EA12
LC83 -> * - - - - - - - - - - - | - - - * - - * - | <-- |lpm_add_sub:1455|addcore:adder|addcore:adder0|result_node4
LC114-> * - - - - - - - - - - - | - - - * - - * - | <-- |lpm_add_sub:1457|addcore:adder|addcore:adder0|result_node4
LC63 -> * - - - - - - - - - - - | - - - * - - * - | <-- |lpm_add_sub:1458|addcore:adder|addcore:adder0|result_node4
LC62 -> * - - - - - - - - - - - | - - - * - - * - | <-- |lpm_add_sub:1460|addcore:adder|addcore:adder0|result_node4
LC59 -> * - - - - - - - - - - - | - - - - - - * - | <-- ~969~1
LC55 -> * - - - - - - - - - - - | - - - - - - * - | <-- ~969~2
LC17 -> - - - - - * - - - - - - | - * - - * - * - | <-- num_add6
LC78 -> - - - - * * - - * - - - | - * - - * - * - | <-- num_add5
LC71 -> - - - * * * - * * - - - | - * - - * - * - | <-- num_add4
LC28 -> - - - * * * * * * - - - | - * - - * - * - | <-- num_add3
LC74 -> - - - * * * * * * - - - | - * - - * - * - | <-- num_add2
LC76 -> - - - * * * * * * - - - | - * - - * - * - | <-- num_add1
LC77 -> - - - * * * * * * - - - | - * - - * - * - | <-- num_add0
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