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MSP430寄存器列表一 作者 wynne 日期 2006-5-10 20:25:00
/************************************************************
* USART 串口寄存器"UCTL","UTCTL","URCTL"定义的各个位 可串口1 串口2公用
************************************************************/
/* UCTL 串口控制寄存器*/
#define PENA 0x80 /*校验允许位*/
#define PEV 0x40 /*偶校验 为0时为奇校验*/
#define SPB 0x20 /*停止位为2 为0时停止位为1*/
#define CHAR 0x10 /*数据位为8位 为0时数据位为7位*/
#define LISTEN 0x08 /*自环模式(发数据同时在把发的数据接收回来)*/
#define SYNC 0x04 /*同步模式 为0异步模式*/
#define MM 0x02 /*为1时地址位多机协议(异步) 主机模式(同步);为0时线路空闲多机协议(异步) 从机模式(同步)*/
#define SWRST 0x01 /*控制位*/
/* UTCTL 串口发送控制寄存器*/
#define CKPH 0x80 /*时钟相位控制位(只同步方式用)为1时时钟UCLK延时半个周期*/
#define CKPL 0x40 /*时钟极性控制位 为1时异步与UCLK相反;同步下降延有效*/
#define SSEL1 0x20 /*时钟源选择位:与SSEL0组合为0,1,2,3四种方式*/
#define SSEL0 0x10 /*"0"选择外部时钟,"1"选择辅助时钟,"2","3"选择系统子时钟 */
#define URXSE 0x08 /*接收触发延控制位(只在异步方式下用)*/
#define TXWAKE 0x04 /*多处理器通信传送控制位(只在异步方式下用)*/
#define STC 0x02 /*外部引脚STE选择位 为0时为4线模式 为1时为3线模式*/
#define TXEPT 0x01 /*发送器空标志*/
/* URCTL 串口接收控制寄存器 同步模式下只用两位:FE和OE*/
#define FE 0x80 /*帧错标志*/
#define PE 0x40 /*校验错标志位*/
#define OE 0x20 /*溢出标志位*/
#define BRK 0x10 /*打断检测位*/
#define URXEIE 0x08 /*接收出错中断允许位*/
#define URXWIE 0x04 /*接收唤醒中断允许位*/
#define RXWAKE 0x02 /*接收唤醒检测位*/
#define RXERR 0x01 /*接收错误标志位*/
/************************************************************
* USART 0 串口0寄存器定义
************************************************************/
#define U0CTL_ 0x0070 /* UART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ 0x0072 /* UART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb U0BR0 = U0BR0_;
#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb U0BR1 = U0BR1_;
#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */
const sfrb U0RXBUF = U0RXBUF_;
#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */
sfrb U0TXBUF = U0TXBUF_;
/* Alternate register names */
#define UCTL0_ 0x0070 /* UART 0 Control */
sfrb UCTL0 = UCTL0_;
#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL0 = UTCTL0_;
#define URCTL0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL0 = URCTL0_;
#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL0 = UMCTL0_;
#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR00 = UBR00_;
#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR10 = UBR10_;
#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF0 = RXBUF0_;
#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF0 = TXBUF0_;
#define UCTL_0_ 0x0070 /* UART 0 Control */
sfrb UCTL_0 = UCTL_0_;
#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL_0 = UTCTL_0_;
#define URCTL_0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL_0 = URCTL_0_;
#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL_0 = UMCTL_0_;
#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR0_0 = UBR0_0_;
#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR1_0 = UBR1_0_;
#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF_0 = RXBUF_0_;
#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF_0 = TXBUF_0_;
/************************************************************
* USART 1 串口1寄存器定义
************************************************************/
#define U1CTL_ 0x0078 /* UART 1 Control */
sfrb U1CTL = U1CTL_;
#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */
sfrb U1TCTL = U1TCTL_;
#define U1RCTL_ 0x007A /* UART 1 Receive Control */
sfrb U1RCTL = U1RCTL_;
#define U1MCTL_ 0x007B /* UART 1 Modulation Control */
sfrb U1MCTL = U1MCTL_;
#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */
sfrb U1BR0 = U1BR0_;
#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb U1BR1 = U1BR1_;
#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */
const sfrb U1RXBUF = U1RXBUF_;
#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */
sfrb U1TXBUF = U1TXBUF_;
#define UCTL1_ 0x0078 /* UART 1 Control */
sfrb UCTL1 = UCTL1_;
#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL1 = UTCTL1_;
#define URCTL1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL1 = URCTL1_;
#define UMCTL1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL1 = UMCTL1_;
#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR01 = UBR01_;
#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR11 = UBR11_;
#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF1 = RXBUF1_;
#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF1 = TXBUF1_;
#define UCTL_1_ 0x0078 /* UART 1 Control */
sfrb UCTL_1 = UCTL_1_;
#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL_1 = UTCTL_1_;
#define URCTL_1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL_1 = URCTL_1_;
#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL_1 = UMCTL_1_;
#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR0_1 = UBR0_1_;
#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR1_1 = UBR1_1_;
#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF_1 = RXBUF_1_;
#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF_1 = TXBUF_1_;
/************************************************************
* ADC12 A/D采样寄存器定义
************************************************************/
/*ADC12转换控制类寄存器*/
#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */
sfrw ADC12CTL0 = ADC12CTL0_;
#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */
sfrw ADC12CTL1 = ADC12CTL1_;
/*ADC12中断控制类寄存器*/
#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */
sfrw ADC12IFG = ADC12IFG_;
#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */
sfrw ADC12IE = ADC12IE_;
#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */
sfrw ADC12IV = ADC12IV_;
/*ADC12存贮器类寄存器*/
#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */
sfrw ADC12MEM0 = ADC12MEM0_;
#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */
sfrw ADC12MEM1 = ADC12MEM1_;
#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */
sfrw ADC12MEM2 = ADC12MEM2_;
#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */
sfrw ADC12MEM3 = ADC12MEM3_;
#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */
sfrw ADC12MEM4 = ADC12MEM4_;
#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */
sfrw ADC12MEM5 = ADC12MEM5_;
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