sw_led.v

来自「FPGA DIY拨码开关实验源码下载」· Verilog 代码 · 共 14 行

module SW_LED(clk_50MHZ,sw,led);

input clk_50MHZ;
input[7:0] sw;
output[7:0] led;

reg[7:0] led;

always @(posedge clk_50MHZ)
begin
	led <= sw;
end 

endmodule