📄 iop.lst
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652 GPAD_D1 equ 2 ;;gpio 4 PIN 1
653 [00] .endif
654
655 [01] .ifnz SPHE8202R_128PIN
656 ;;wurh note:only for 8202R 64M SDRAM GAME PAD(GAME_GPIO_INTERFACE_TYPE1)
657 ;;16M SDRAM need change D1 port(GAME_GPIO_INTERFACE_TYPE2)
658 0002 GPAD_PORT_CLK equ GPIO_PORT2 ;;for CLK
659 0002 GPAD_PORT_LATCH equ GPIO_PORT2 ;;for LATCH
660 0003 GPAD_PORT_D0 equ GPIO_PORT3 ;; for D0
661 0003 GPAD_PORT_D1 equ GPIO_PORT3 ;; for D1
662
663 000A GPAD_PORT_CFG_CLK equ GPIO_IO2_CFG
664 000A GPAD_PORT_CFG_LATCH equ GPIO_IO2_CFG
665 000B GPAD_PORT_CFG_D0 equ GPIO_IO3_CFG
666 000B GPAD_PORT_CFG_D1 equ GPIO_IO3_CFG
667
668
669 0005 GPAD_CLK equ 5 ;;gpio 21 PIN 9
670 0004 GPAD_LATCH equ 4 ;;gpio 20 PIN 8
671 0005 GPAD_D0 equ 5 ;;gpio 29 PIN 52
672 0002 GPAD_D1 equ 2 ;;gpio 10 PIN 123
Mon Jun 04 13:40:38 2007 Page 13
673 [00] .endif
674
675 [01] .if SPHE8200
676 ;;ljd change for 28.29.31.70(gpio) 03/09/17
677
678 GPAD_PORT_CLK equ GPIO_PORT0 ;;for CLK
679 GPAD_PORT_LATCH equ GPIO_PORT4 ;;for LATCH
680 GPAD_PORT_D0_D1 equ GPIO_PORT0 ;; for D0,D1
681
682 GPAD_PORT_CFG_CLK equ GPIO_IO0_CFG
683 GPAD_PORT_CFG_LATCH equ GPIO_IO4_CFG
684 GPAD_PORT_CFG_D0_D1 equ GPIO_IO0_CFG
685
686 GPAD_CFG_CLK equ %00010000
687 GPAD_CFG_LATCH equ %00001000
688 GPAD_CFG_D0_D1 equ %11110011
689
690 GPAD_CLK equ 4 ;;gpio 4 PIN 31
691 GPAD_LATCH equ 3 ;;gpio 3 PIN 70
692 GPAD_D1 equ 3 ;;gpio 3 PIN 29
693 GPAD_D0 equ 2 ;;gpio 2 PIN 28
694 [00] .endif
695
696 ;;*********************************
697 ;;IR_IN
698 ;;*********************************
699 [01] .if SPHE8202
700 [02] .ifnz SPHE8202L_128PIN
701 IR_PORT equ GPIO_PORT1
702 IR_PORT_CFG equ GPIO_IO1_CFG
703 IR_IN equ %00000010 ;;gpio 9
704 IR_IN_bit equ 1
705 [02] .else
706 [03] .ifnz SPHE8202R_128PIN
707 0002 IR_PORT equ GPIO_PORT2
708 000A IR_PORT_CFG equ GPIO_IO2_CFG
709 0008 IR_IN equ %00001000 ;;gpio 19
710 0003 IR_IN_bit equ 3
711 [03] .else
712 IR_PORT equ GPIO_PORT2
713 IR_PORT_CFG equ GPIO_IO2_CFG
714 IR_IN equ %00010000 ;;gpio 20
715 IR_IN_bit equ 4
716 [02] .endif
717 [01] .endif
718 [00] .endif
719
720 [01] .if SPHE8200
721 IR_PORT equ GPIO_PORT6
722 IR_PORT_CFG equ GPIO_IO6_CFG
723 IR_IN equ %00100000 ;;gpio 56
724 IR_IN_bit equ 5
725 [00] .endif
726
727 0080 IR_READY equ %10000000
728 0040 IR_REPEAT equ %01000000
729 0020 IR_REPLACE equ %00100000
Mon Jun 04 13:40:38 2007 Page 14
730
731 ;;IR process state
732 0000 IR_CHK_HEAD equ 0
733 0001 IR_CHK_OFF equ 1
734 0002 IR_CHK_ADDR_DAT equ 2
735
736 ;;NEC IR bit keep length
737 000B IR_MAX_TWO_DATA_LEN equ (9+2) ;;=108ms/12ms
738 006B IR_MAX_PULSE_LEN equ (10000*12)/1120 ;;12 ms
739 0040 IR_HEAD_PULSE_LEN equ (9000*8)/1120 ;;72 ms
740 0020 IR_OFF_PULSE_LEN equ (4500*8)/1120 ;;40 ms
741 0011 IR_REP_PULSE_LEN equ (2500*8)/1120 ;;20 ms
742 0003 IR_LOW_PULSE equ 3 ;;560us
743 000A IR_HI_PULSE equ 10 ;;1680us
744
745 ;;PHILIPS
746 0035 IR1_MAX_TWO_DATA_LEN equ (50+3) ;;=108ms/2.128ms
747 0013 IR1_MAX_PULSE_LEN equ (16+3) ;;+ 3*112us
748 000B IR1_PULSE_LEN_MAX equ (8+3) ;;+ 3*112us
749 000B IR1_PULSE_LEN equ (8+3) ;;+ 3*112us
750 0005 IR1_PULSE_LEN_MIN equ (8-3) ;;+ 3*112us
751
752 ;;THOMSON
753 [01] .ifnz IR_THOMSON
754 IR_MARK_STATE equ 1
755 IR_SPACE_STATE equ 2
756 IR_SYNC_STATE equ 3
757 IR_BIT01_STATE equ 4
758 BEGIN_FROM_HEAD equ 5
759 [00] .endif
760
761 ;;M50560
762 [01] .ifnz IR_M50560
763 BEGIN_FROM_HEAD equ 1
764 IR_MARK_STATE equ 2
765 IR_SPACE_STATE equ 3
766 IR_SYNC_STATE equ 4
767 IR_BIT01_STATE equ 5
768 IR_4MSLOW_STATE equ 6
769 [00] .endif
770
771 ;;IR_AS1213
772 [01] .ifnz IR_AS1213
773 BEGIN_FROM_HEAD equ 1
774 IR_MARK_STATE equ 2
775 IR_SPACE_STATE equ 3
776 IR_SYNC_STATE equ 4
777 IR_BIT01_STATE equ 5
778 IR_REPEAT_STATE equ 6
779 [00] .endif
780
781 ;;IR_M3004
782 [01] .ifnz IR_M3004
783 IR_IDLE_STATE equ 0
784 IR_HIGH_STATE equ 1
785 IR_LOW_STATE equ 2
786
Mon Jun 04 13:40:38 2007 Page 15
787 BIT_1_TOP equ (80*1000)/400
788 BIT_1_BOTTOM equ (70*1000)/400
789 BIT_0_TOP equ (55*1000)/400
790 BIT_0_BOTTOM equ (45*1000)/400
791 [00] .endif
792
793 ;;IR_KONKA
794 [01] .ifnz IR_KONKA
795 STATE_IDLE equ 0
796 STATE_3MS_LOW equ 1
797 STATE_3MS_HIGH equ 2
798 STATE_0_5MS_LOW equ 3
799 STATE_BIT01 equ 4
800
801 MASK_LEN equ 23
802 SPACE_LEN equ 23
803 SYNC_LEN equ 4
804 BIT0_LEN equ 11
805 BIT1_LEN equ 20
806 REPEAT_LEN equ 255
807 [00] .endif
808
809 ;;IR_TDP101
810 [01] .ifnz IR_TDP101
811 STATE_IDLE equ 0 ;; idle state
812 STATE_PRE_CODE_1 equ 1 ;; 4.22ms low
813 STATE_PRE_CODE_2 equ 2 ;; 2.11ms high
814 STATE_PRE_CODE_3 equ 3 ;; 2.11ms low
815 STATE_PRE_CODE_4 equ 4 ;; 4.22ms high
816 STATE_BIT_LOW equ 5 ;; 0.5275ms low
817 STATE_BIT_HIGH equ 6 ;; 0.527ms/1.5825 high
818 ;;------------------------------------------------------------------------------------
819 LEN_PRE_CODE_1 equ 30 ;; 4.22ms /0.112ms
820 LEN_PRE_CODE_2 equ 14 ;; 2.11ms /0.112ms
821 LEN_PRE_CODE_3 equ 14 ;; 2.11ms /0.112ms
822 LEN_PRE_CODE_4 equ 30 ;; 4.22ms /0.112ms
823 LEN_REPEAT equ 14 ;; 2.11ms /0.112ms
824 LEN_BIT_LOW equ 2 ;; 0.5275ms/0.112ms
825 LEN_BIT_IS_1 equ 10 ;; 1.5825 /0.112ms
826 LEN_BIT_IS_0 equ 2 ;; 0.527ms/0.112ms
827 LEN_SEPARATE equ 140 ;; 16.88ms/0.112ms
828 [00] .endif
829
830
831 ;;==============================================================================
832 [01] .ifnz PCA9564
833 ;;==============================================================================
834 PCA9564_WR_bit equ 3 ;;GPIO 35 (8202 256PIN)
835 PCA9564_RD_bit equ 4 ;;GPIO 36 (8202 256PIN)
836 PCA9564_CE_bit equ 5 ;;GPIO 37 (8202 256PIN)
837 PCA9564_A0_bit equ 0 ;;GPIO 32 (8202 256PIN)
838 PCA9564_A1_bit equ 1 ;;GPIO 33 (8202 256PIN)
839 PCA9564_INT_bit equ 0 ;;GPIO 48 (8202 256PIN)
840 PCA9564_RESET_bit equ 1 ;;GPIO 49 (8202 256PIN)
841 ;;==============================================================================
842 PCA9564_WR_CFG equ GPIO_IO4_CFG
843 PCA9564_RD_CFG equ GPIO_IO4_CFG
Mon Jun 04 13:40:38 2007 Page 16
844 PCA9564_CE_CFG equ GPIO_IO4_CFG
845 PCA9564_A0_CFG equ GPIO_IO4_CFG
846 PCA9564_A1_CFG equ GPIO_IO4_CFG
847 PCA9564_INT_CFG equ GPIO_IO6_CFG
848 PCA9564_RESET_CFG equ GPIO_IO6_CFG
849 PCA9564_DATA_CFG equ GPIO_IO5_CFG
850 ;;==============================================================================
851 PCA9564_WR_PORT equ GPIO_PORT4
852 PCA9564_RD_PORT equ GPIO_PORT4
853 PCA9564_CE_PORT equ GPIO_PORT4
854 PCA9564_A0_PORT equ GPIO_PORT4
855 PCA9564_A1_PORT equ GPIO_PORT4
856 PCA9564_INT_PORT equ GPIO_PORT6
857 PCA9564_RESET_PORT equ GPIO_PORT6
858 PCA9564_DATA_PORT equ GPIO_PORT5
859 ;;==============================================================================
860 PCA9564_beginning_state equ 0
861 PCA9564_continue_Receive_data_state equ 1
862 PCA9564_Receive_Judge_SI_state equ 2
863 PCA9564_continue_Transmit_data_state equ 3
864 PCA9564_Transmit_Judge_SI_state equ 4
865
866 MAX_RX_BUF_LEN equ 64
867 MAX_TX_BUF_LEN equ 64
868 [00] .endif
869
870
871
872
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