boot_sim.s

COG-VP12864液晶屏驱动代码及对应RTC实例

/*
*************************************************************************
*									*
*                                                                       *
*  boot.s: This file contants application startup and initializaton 	*
*          code.							*
*									*
*									*
*  Assembly: eas boot.s							*
*                                                                       *
*                                                                       *
*************************************************************************
*                                                                       *
*  Copyright 1992-1994, Embedded Performance, Inc.  All Rights Reserved	*
*									*
*  A purchaseing customer is hearby granted rights to modify and 	*
*  distribute in binary and source form.				*
*                                                                       *
*************************************************************************
*/
#include "include\asm.h"
#include "include\mipsreg.h"
#include "include\cpureg.h"
#include "include\soc.h"
#include "include\cache.h"
#include "include\stackframe.h"

	.text
	.globl 	_start
	.ent 	_start

	.extern ExceptionProcess
	.extern main
	.frame 	sp,24,zero
	
_start:
	.set    noreorder
	.set 	noat
	nop
	b	boot
	nop
	#--- VegaII exception handler, offset 200 
	.align	8	# force next address to multiple of 0x100
	.word	0
	.align  8	# 0xbfc00200

	b	ExceptionProcess		# TLB miss:	bfc00200
	nop
	.align  7		# should have TLB handler eventually
	b	ExceptionProcess		# XTLB miss:	bfc00280
	nop
	.align	8		# force next address to bfc00300
	b	ExceptionProcess		# CACHE ERROR, chained to rtc_inteption
	nop
	.align	7		# force next address to bfc00380
	b	ExceptionProcess 	# General Exception
	nop
	.align  8		# force next address to bfc00400
	b	ExceptionProcess		# interrupts if cause_iv=1
	nop
	.align	7		# force next address to bfc00480
	b	ExceptionProcess		# cache 
	nop

boot: 
/* config register */
	#--- set the global data pointers
	la		gp,_gp
	li  	sp, 0xa0400000		#--- no cache L/S
	nop
	nop
    
/*------------------------------------------------------------------------------
 	Entry point for boot code.
----------------------------------------------------------------------------*/
StartUp:
/* disable watch exception */
    mtc0    zero, CP0_WATCHLO
    nop
    nop
	li      t0, 0x00410000	#--- BEV=bootstrap, Mask all interrupts, IE=disabled 
	mtc0    t0, CP0_STATUS
	nop

/* R4300 initialization */
	lui    	t0,0x0006		# start with default val
	nop
	ori     t0,t0,0x6462	# Little Endian, Cache Off
	nop
	mtc0    t0,CP0_CONFIG      #- config <- 0x00066462 - No Cache
	nop			   		# 0x00066463 - With Cache
	nop

	mtc0	zero,CP0_CAUSE		# clear s/w interrupts
	nop
	nop
/* set Sdram mode */
	li		a0,0x1ff807cc
	li		a2,0xa0000000	
	or		a0,a2,a0     	
	li		t1,0x02     	
	sb		t1,0x2(a0)  
	li		t1,0x2b 
	sb		t1,(a0) 
	li		t1,0x80 
	sb		t1,0x1(a0)
/* wait 1000 ns loading data to sdram */
	nop
	
noCached:
/* init ram */
	li 		a0, 0x100		/* data number(word width) which need init */
	li 		a1, 0x1fc10000	/* src address */
	li 		a2, 0x00500000	/* dest address */
	li 		t0, 0xa0000000	/* no cache L/S */
	or 		a1, a1, t0
	or 		a2, a2, t0	
	li 		t0, 0x0
1:
	lw 		t1, 0x0(a1)
	addi 	a1, a1, 0x4
	sw 		t1, 0x0(a2)
	addi 	t0, 0x1
	bne 	t0, a0, 1b
	addi 	a2, a2, 0x4	/* delay slot */
	nop	

/* enable interrupts */
	mtc0	zero,CP0_CAUSE		# clear s/w interrupts
	nop
	STI
	nop
	mfc0	t0, CP0_STATUS
	nop
	ori		t0, STATUSF_IP4
	mtc0	t0, CP0_STATUS
	nop

/* entry user's main */	
	#--- call user's main passing two parameters: main(argc, argv)
	jal	main
	nop

	# if we return then user is exiting with status 0
	li		a0,0
	nop
	addiu	zero,zero,0		/* sim test end */
	nop
	
	j	exit		/* all done, exit with no error */
	nop
	.end start