boot_fpga.s

COG-VP12864液晶屏驱动代码及对应RTC实例

/*
*************************************************************************
*									*
*                                                                       *
*  boot.s: This file contants application startup and initializaton 	*
*          code.							*
*									*
*									*
*  Assembly: eas boot.s							*
*                                                                       *
*                                                                       *
*************************************************************************
*                                                                       *
*  Copyright 1992-1994, Embedded Performance, Inc.  All Rights Reserved	*
*									*
*  A purchaseing customer is hearby granted rights to modify and 	*
*  distribute in binary and source form.				*
*                                                                       *
*************************************************************************
*/
#include "include\asm.h"
#include "include\mipsreg.h"
#include "include\cpureg.h"
#include "include\soc.h"
#include "include\cache.h"
#include "include\stackframe.h"

	.text
	.globl 	_start
	.ent 	_start

	.extern ExceptionProcess
	.extern main
	.frame 	sp,24,zero
	
_start:
	.set    noreorder
	.set 	noat
	nop
	b	boot
	nop
	#--- VegaII exception handler, offset 200 
	.align	8	# force next address to multiple of 0x100
	.word	0
	.align  8	# 0xbfc00200

	b	ExceptionProcess		# TLB miss:	bfc00200
	nop
	.align  7		# should have TLB handler eventually
	b	ExceptionProcess		# XTLB miss:	bfc00280
	nop
	.align	8		# force next address to bfc00300
	b	ExceptionProcess		# CACHE ERROR, chained to rtc_inteption
	nop	
	.align	7		# force next address to bfc00380
	nop
	b   ExceptionProcess	 	# General Exception
	nop	
	.align  8		# force next address to bfc00400
	b	ExceptionProcess		# interrupts if cause_iv=1
	nop
	.align	7		# force next address to bfc00480
	b	ExceptionProcess		# cache 
	nop

boot: 
/* config register */
	#--- set the global data pointers
	la	gp,_gp
	li  sp, 0x80400000

	nop
	nop
    
/*------------------------------------------------------------------------------
 	Entry point for boot code.
----------------------------------------------------------------------------*/
StartUp:
/* disable watch exception */
    mtc0    zero, CP0_WATCHLO
    nop
    nop
	li      t0, 0x00410000	#--- BEV=bootstrap, Mask all interrupts, IE=disabled 
	mtc0    t0, CP0_STATUS
	nop

/* R4300 initialization */
	lui     t0,0x0006		# start with default val
	nop
	ori     t0,t0,0x6463	# Little Endian, Cache On
	nop
	mtc0    t0,CP0_CONFIG      #- config <- 0x00066462 - No Cache
	nop			   		# 0x00066463 - With Cache
	nop

	mtc0	zero,CP0_CAUSE		# clear s/w interrupts
	nop
	nop
	
	jal		InitDebugSerial
	nop
	
	li		a0,0x61				#-- 'a'
	jal		WriteDebugByte
	nop	
	
	la		t0,InitSDRAM
	li		t1,0xa0000000
	or		t0,t1
	jalr	t0
	nop

	/*
	la		t0,InitSDRAMType
	li		t1,0xa0000000
	or		t0,t1
	jalr	t0
	nop
	*/
	li	v0,0x47
	
	or		a0,zero,v0		#-- sdram type
	jal		WriteDebugByte
	nop	
	
	li		a0,0x62			#-- 'b'
	jal		WriteDebugByte
	nop

/* call kernel's CacheInit function */
	la      t0, CacheInit
	li      t1, 0xA0000000
	or      t0, t0, t1		#--  make sure we're running uncached
	jalr    t0			#-- before calling CacheInit.
	nop

/* zero out the Instruction and Data cache tags since line size is different
   from what kernel assumes... */
	mtc0    zero, CP0_TAGLO		#-- zero-out the primary cache tag
	nop
	nop

/* zero out the Instruction cache tags */
	li  t0, 0x80000000
	li  t1, 0x80004000		#-- 16k Instruction Cache
InitICacheTag:
	cache   INDEX_STORE_TAG_I, 0(t0)
	addu    t0, t0, 0x20		#--line size is 32 bytes
	bne     t0, t1, InitICacheTag
	nop

/* zero out the Data cache tags */
	li  t0, 0x80000000
	li  t1, 0x80002000		#-- 8k Data cache
InitDCacheTag:
	cache   INDEX_STORE_TAG_D, 0(t0)
	addu    t0, t0, 0x10		#-- line size is 16 bytes
	bne     t0, t1, InitDCacheTag
	nop

	li		a0,0x63			#-- 'c'
	jal		WriteDebugByte
	nop
/* Switch execution cached, un-mapped region. */
cached:
/* init ram, Size = 0x200(BYTE)*/
	li a0, 0x200		/* data number(word width) which need init */
	li a1, 0x1fc10000	/* src address */
	li a2, 0x00500000	/* dest address */
	li t0, 0xa0000000	/* cached L/S */
	or a1, a1, t0
	or a2, a2, t0
	li t0, 0x0
1:
	lw   t1, 0x0(a1)
	addi a1, a1, 0x4
	sw   t1, 0x0(a2)
	addi t0, 0x1
	bne  t0, a0, 1b
	addi a2, a2, 0x4	/* delay slot */
	nop	

	li		a0,0x64			#-- 'd'
	jal		WriteDebugByte
	nop
	
/* enable interrupts */
	mtc0	zero,CP0_CAUSE		# clear s/w interrupts
	nop
	nop
	mfc0	t0, CP0_STATUS
	nop
	ori		t0, STATUSF_IP4|ST0_IE
	mtc0	t0, CP0_STATUS
	nop

/* entry user's main */	
	#--- call user's main passing two parameters: main(argc, argv)
	la      t0, main
	li      t1, 0x9fffffff		# we will run cached
	and     t0, t0, t1			
	jalr    t0			
	nop 
	/*
	jal	main
	nop
	*/

	# if we return then user is exiting with status 0
	li	a0,0
	nop
	addiu	zero,zero,0
	nop
	j	exit		/* all done, exit with no error */
	nop
	.end start