arksoc.h

COG-VP12864液晶屏驱动代码及对应RTC实例

/*
********************************************************
// Copyright (c)2002 Ark Pioneer Microelectronics Ltd., 
   All Rights Reserved
// Filename: arksoc.h
// Version: 0.1
// Created: 01.09.2004
// By: Danny
*******************************************************
// Description: Generic ARK SoC memory space and registers
//		definitions
*******************************************************
// Revision History:
// Rev 002:
// Date: 01.12.2004
// By: danny
// Description: 
//	1. Modified RTC Register Base and Access way (Hotter modified his struct)
//	2. ICU Base was change to 0x1ff00000
//	3. Added LPC_SUPERIO_REGISTER_BASE	0x1ff10000	// LPC SuperIO Mem Base(Keyboard MOUSE)
//	4. Added LPC_REGISTER_BASE		0x1ff20000
//	5. Deleted old LPC Module definition
//	6. Added P4032_ICU_REGISTER_BASE	0x1ff90000	// P4032 Interrupt Control Registers
//
// Revision History:
// Rev 001:
// Date: 01.09.2004
// Created: danny
*********************************************************
*/

#ifndef _ARKSOC_H_
#define _ARKSOC_H_

#ifdef __cplusplus
extern "C" {
#endif

//******* Soc Memory Space Definitions *******//
#define DRAM_MEM_SPACE_BASE		0x00000000		// 64M P4032 DRAM Memory Base
#define SDRAM_MEM_SPACE_BASE		0x04000000		// 64M SDRAM Memory Base
#define FLASH_MEM_SPACE_BASE		0x08000000		//128M Flash & SDRAM Share Space Base
#define MIRROR_ROM_MEM_SPACE_BASE	0x08000000		//  2M Boot Rom Mirror Space Base
#define PCI_MEM_SPACE_BASE		0x10000000		//128M P4032 PCI memory space Base
#define LCD_MEM_SPACE_BASE		0x18000000		// 32M LCD & HIGH SPEED BUS Memory Space Base
#define ISA_MEM_SPACE_BASE		0x1A000000		// 32M ISA Bus Memory Space Base
#define ISA_IO_SPACE_BASE		0x1C000000		// 32M ISA Bus I/O Space Base
#define PCI_IO_SPACE_BASE		0x1ed00000		//  1M P4032 PCI IO Space Base
#define PCI_CONF_SPACE_BASE		0x1ee00000		//  1M P4032 PCI Config Space Base
#define V96XPBC_BASE			0x1ef00000		// 64K P4032 V96xPBC Base
#define BOOT_ROM_MEM_BASE		0x1fc00000		//  2M Boot Rom Space Base

#define ICU_REGISTER_BASE		0x1ff00000		// P4032 Intterupt Control Unit Registers
#define RTC_REGISTER_BASE		0x1ff08000		// Real time clock "Pointer" register
#define LPC_SUPERIO_REGISTER_BASE	0x1ff10000		// LPC SuperIO Mem Base(Keyboard MOUSE)
#define LPC_REGISTER_BASE		0x1ff20000		// LPC (Keyboard MOUSE)
#define LED_REGISTER_BASE		0x1ff20020		// LED & I2C and I2S display cells 
#define FLEXIO_REGISTER_BASE		0x1ff30000		// GPIF Block
#define GPIO_BASE			0x1ff40000		// Generic IO Register
#define SOC_CONFIG_REGISTER_BASE	0x1ff807c0		// Ark SOC Configration Space
#define SOC_EXTEND_BASE			0x1ff80800		// For Soc Extended Space
#define UART2_REGISTER_BASE		0x1ff80BE0		// COM2 serial port Registers
#define UART1_REGISTER_BASE		0x1ff80DE0		// COM1 serial port Registers
#define CENTRONIC_PORT_REGISTER_BASE	0x1ff80fe0		// P4032 Centronic port Registers
#define P4032_ICU_REGISTER_BASE		0x1ff90000		// P4032 Interrupt Control Registers
#define FDC_REGISTER_DACK		0x1ffa0000		// P4032 Floppy Disk Control Registers
#define BCR_REGISTER_BASE		0x1ffb0000		// P4032 Board Control Unit Registers
#define DCR_REGISTER_BASE		0x1ffc0000		// P4032 DRAM Control Unit Registers
#define OPTION_REGISTER_BASE		0x1ffd0000		// P4032 Option Registers

//******* P4032 Original Definitions *******//
/* NS16550 parameters & (endian independent) register layout */
#define NS16550_HZ	(24000000/13)
#ifdef ASM_ONLY
#define NSREG(x)	((x)*4)
#define NS16550_INB(dst,offs,base) \
	lw	dst,offs(base)
#define NS16550_OUTB(src,offs,base) \
	sw	src,offs(base)
#endif

/* DRAM control register (8 bits, 1 word per bit) */
#define DCR_SIMM1_DRAM	0x80	/* simm1 is DRAM */
#define DCR_TYPE	0x60	/* simm0/1 type */
#define  DCR_BURSTEDO	 0x60	  /* burst edo */
#define  DCR_EDO	 0x40	  /* normal edo */
#define  DCR_FASTPAGE1	 0x20	  /* fast page mode */
#define  DCR_FASTPAGE2	 0x00	  /* fast page mode */
#define DCR_DRAMFAST	0x10	/* select fast(60ns)/slow(70ns) DRAM timings */
#define DCR_SIMM1_SGL	0x08	/* simm1 is single-sided */
#define DCR_SIMM0_SGL	0x04	/* simm0 is single-sided */
#define DCR_SIMM0_SIZE	0x03	/* simm0 size (x2 if double-sided) */
#define  DCR_4MB	 0x1
#define  DCR_8MB	 0x2
#define  DCR_16MB	 0x3

/* Board option links */
#define OPTION_SIMM1	0x80	/* see DCR_SIMM1_DRAM */
#define OPTION_DRAMTYPE	0x60	/* see DCR_TYPE */
#define OPTION_DRAMFAST	0x10	/* see DCR_DRAMFAST */
#define OPTION_BE	0x08	/* endianness */
#define OPTION_ENVNRST	0x04	/* ~ force env reset */
#define OPTION_USER	0x03
#define OPTION_USER1	0x02
#define OPTION_USER0	0x01

/* Board control register (8 bits, 1 word per bit) */
#define BCR_FLASH_WE	0x80 	/* flash prom write enable */
#define BCR_IO_LE	0x40	/* little-endian i/o system */
#define BCR_ETH_ENABLE	0x20 	/* ethernet chip enable (!reset) */
#define BCR_FDC_TC	0x10 	/* floppy dma terminal count */
#define BCR_SCSI_ENABLE	0x08	/* scsi chip enable (!reset) */
#define BCR_LED_ON	0x04	/* led on (!blank) */
#define BCR_AUTO_BUSY	0x02	/* enable auto busy generation */
#define BCR_V96X_ENABLE	0x01	/* enable V96x pci chip (!reset) */

/* P4032 local to PCI bus apertures are set up with the following sizes */
#define PCI_MEM_SPACE_SIZE	(128 * 1024 * 1024)
#define PCI_IO_SPACE_SIZE	(  1 * 1024 * 1024)
#define PCI_CONF_SPACE_SIZE	(  1 * 1024 * 1024)

/* PCI i/o region in PCI space */
#define PCI_IO_SPACE_PCI_BASE		0x00000000

/* PCI mem regions in PCI space (new configuration) */
#define PCI_MEM_SPACE_PCI_BASE		0x10000000

#ifdef __cplusplus
}
#endif

#endif /* _ARKSOC_H_ */