📄 cache.h
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#ifndef _CACHE_H_
#define _CACHE_H_
/* flush_cache types */
#define ICACHE 0x00
#define DCACHE 0x01
#define IADDR 0x02
/*
// Define R4000 primary cache states.
*/
#define PRIMARY_CACHE_INVALID 0x0 /* primary cache invalid */
#define PRIMARY_CACHE_SHARED 0x1 /* primary cache shared (clean or dirty) */
#define PRIMARY_CACHE_CLEAN_EXCLUSIVE 0x2 /* primary cache clean exclusive */
#define PRIMARY_CACHE_DIRTY_EXCLUSIVE 0x3 /* primary cache dirty exclusive */
/*
// Define R4000 system coprocessor register bit field offsets.
*/
#define INDEX_INDEX 0x0 /* TLB specified index <5:0> */
#define INDEX_PROBE 0x1f /* TLB probe failure <31> */
#define RANDOM_INDEX 0x0 /* TLB random index <5:0> */
#define ENTRYLO_G 0x0 /* Global <0> */
#define ENTRYLO_V 0x1 /* Valid <1> */
#define ENTRYLO_D 0x2 /* Dirty <2> */
#define ENTRYLO_C 0x3 /* Cache control <5:3> */
#define ENTRYLO_PFN 0x6 /* Page Frame <29:6> */
#define PAGEMASK_PAGEMASK 0xd /* Page mask <24:13> */
#define WIRED_NUMBER 0x0 /* Wired entries <5:0> */
#define ENTRYHI_PID 0x0 /* Process id <7:0> */
#define ENTRYHI_VPN2 0xd /* Virtual page <31:13> */
#define PID_MASK 0xfff /* allow for ample expansion */
#define PSR_IE 0x0 /* Interrupt enable <0> */
#define PSR_EXL 0x1 /* Exception level <1> */
#define PSR_ERL 0x2 /* Error level <2> */
#define PSR_KSU 0x3 /* Kernel/supervisor/user <4:3> */
#define PSR_PMODE (PSR_KSU + 1) /* Previous mode bit <4> */
#define PSR_UX 0x5 /* User extended <5> */
#define PSR_SX 0x6 /* Supervior extended <6> */
#define PSR_KX 0x7 /* Kernel extended <7> */
#define PSR_INTMASK 0x8 /* Interrupt mask <15:8> */
#define PSR_DE 0x10 /* Disable cache parity and ECC <16> */
#define PSR_CE 0x11 /* Check enable <17> */
#define PSR_CH 0x12 /* Cache hit <18> */
#define PSR_SR 0x14 /* Soft reset <20> */
#define PSR_TS 0x15 /* TLB shutdown <21> */
#define PSR_BEV 0x16 /* Bootstrap exception vector <22> */
#define PSR_CU0 0x1c /* Coprocessor 0 enabled <28> */
#define PSR_CU1 0x1d /* Coprocessor 1 enabled <29> */
#define PSR_CU2 0x1e /* Coprocessor 2 enabled <30> */
#define PSR_CU3 0x1f /* Coprocessor 3 enabled <31> */
/* */
#define CONFIG_K0 0x0 /* Kseg0 cache algorithm <2:0> */
#define CONFIG_CU 0x3 /* Update on store conditional <3> */
#define CONFIG_DB 0x4 /* Data cache block size <4> */
#define CONFIG_IB 0x5 /* Instruction cache block size <5> */
#define CONFIG_DC 0x6 /* Data cache size <8:6> */
#define CONFIG_IC 0x9 /* Instruction cache size <11:9> */
#define CONFIG_EB 0xd /* Block ordering <13> */
#define CONFIG_EM 0xe /* ECC mode enable <14> */
#define CONFIG_BE 0xf /* Big endian memory <15> */
#define CONFIG_SM 0x10 /* Use dirty shared state <16> */
#define CONFIG_SC 0x11 /* Secondary cache present <17> */
#define CONFIG_EW 0x12 /* System address port width <19:18> */
#define CONFIG_SW 0x14 /* Secondary cache port width <20> */
#define CONFIG_SS 0x15 /* Split secondary cache mode <21> */
#define CONFIG_SB 0x16 /* Secondary cache block size <23:22> */
#define CONFIG_EP 0x18 /* Pattern for write back data <27:24> */
#define CONFIG_EC 0x1c /* System address port clock ratio <30:28> */
#define CONFIG_CM 0x1f /* Master checker mode <31> */
#define ECC_ECC 0x0 /* Secondary cache ECC <7:0> */
#define CACHEERR_PIDX 0x0 /* Primary cache index <2:0> */
#define CACHEERR_SIDX 0x3 /* Secondary cache index <21:3> */
#define CACHEERR_EI 0x18 /* ECC error on pimary store miss <24> */
#define CACHEERR_EB 0x19 /* Data error on instrruction error <25> */
#define CACHEERR_EE 0x1a /* Error on system address bus <26> */
#define CACHEERR_ES 0x1b /* Error accessing processor state <27> */
#define CACHEERR_ET 0x1c /* Error on tag field <28> */
#define CACHEERR_ED 0x1d /* Error on data field <29> */
#define CACHEERR_EC 0x1e /* Cache level of error <30> */
#define CACHEERR_ER 0x1f /* Type of reference <31> */
#define TAGLO_P 0x0 /* primary tag even parity <0> */
#define TAGLO_PSTATE 0x6 /* primary cache state <7:6> */
#define TAGLO_PTAGLO 0x8 /* primary tag low physical address <31:8> */
/*
# Define R4000 cache instruction operation codes.
*/
#define INDEX_INVALIDATE_I 0x0 /* invalidate primary instruction cache*/
#define INDEX_WRITEBACK_INVALIDATE_D 0x1 /* writeback/invalidate primary data cache*/
#define INDEX_INVALIDATE_SI 0x2 /* invalidate secondary instruction cache*/
#define INDEX_WRITEBACK_INVALIDATE_SD 0x3 /* writeback/invalidate secondary data cache*/
#define INDEX_LOAD_TAG_I 0x4 /* load primary instruction tag indexed*/
#define INDEX_LOAD_TAG_D 0x5 /* load primary data tag indexed*/
#define INDEX_LOAD_TAG_SI 0x6 /* load secondary instruction tag indexed*/
#define INDEX_LOAD_TAG_SD 0x7 /* load secondary data tag indexed*/
#define INDEX_STORE_TAG_I 0x8 /*store primary instruction tag indexed */
#define INDEX_STORE_TAG_D 0x9 /* store primary data tag indexed */
#define INDEX_STORE_TAG_SI 0xa /* store secondary instruction tag indexed*/
#define INDEX_STORE_TAG_SD 0xb /* store secondary data tag indexed*/
#define CREATE_DIRTY_EXCLUSIVE_D 0xd /* create dirty exclusive primary data cache*/
#define CREATE_DIRTY_EXCLUSIVE_SD 0xf /* create dirty exclusive secondary data cache*/
#define HIT_INVALIDATE_I 0x10 /* invalidate primary instruction cache*/
#define HIT_INVALIDATE_D 0x11 /* invalidate primary data cache*/
#define HIT_INVALIDATE_SI 0x12 /* invalidate secondary instruction cache*/
#define HIT_INVALIDATE_SD 0x13 /* invalidate secondary data cache*/
#define HIT_WRITEBACK_INVALIDATE_D 0x15 /* writeback/invalidate primary data cache*/
#define HIT_WRITEBACK_INVALIDATE_SD 0x17 /* writeback/invalidate secondary data cache*/
#define HIT_WRITEBACK_D 0x19 /* writeback primary data cache*/
#define HIT_WRITEBACK_SD 0x1b /* writeback secondary data cache*/
#define HIT_SET_VIRTUAL_SI 0x1e /* hit set virtual secondary instruction cache*/
#define HIT_SET_VIRTUAL_SD 0x1f /* hit set virtual secondary data cache*/
#endif
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