📄 c8051f200_cy.h
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This bit controls the division of the system clock supplied to Timer 2. This bit is ignored
when the timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).
=0 : Timer 2 uses the system clock divided by 12.
=1 : Timer 2 uses the system clock.
CKCON.4 =T1M : Timer 1 Clock Select.
This bit controls the division of the system clock supplied to Timer 1.
=0 : Timer 1 uses the system clock divided by 12.
=1 : Timer 1 uses the system clock.
CKCON.3 =T0M : Timer 0 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 0.
=0 : Counter/Timer uses the system clock divided by 12.
=1 : Counter/Timer uses the system clock.
CKCON.2_0 =UNUSED. Read = 000b, Write = don.t care.
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PCON.7 =SMOD : Serial Port Baud Rate Doubler Enable.
=0 : Serial Port baud rate is that defined by Serial Port Mode in SCON.
=1 : Serial Port baud rate is double that defined by Serial Port Mode in SCON.
PCON.6_2 =GF4-GF0 : General Purpose Flags 4-0.
These are general purpose flags for use under software control.
PCON.1 =STOP : Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode.
This bit will always be read as 0.
=1 : Goes into power down mode. (Turns off oscillator).
PCON.0 =IDLE : Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
=1 : Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
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SPI0CFG.7 =CKPHA : SPI Clock Phase This bit controls the SPI clock phase.
=0 : Data sampled on first edge of SCK period.
=1 : Data sampled on second edge of SCK period.
SPI0CFG.6 =CKPOL : SPI Clock Polarity. This bit controls the SPI clock polarity.
=0 : SCK line low in idle state.
=1 : SCK line high in idle state.
SPI0CFG.5_3 =BC2-BC0: SPI Bit Count. Indicates which of the up to 8 bits of the SPI word have been transmitted
(R) =000 0bit
=001 1bit
=010 2bit
=011 3bit
=100 4bit
=101 5bit
=110 6bit
=111 7bit
SPI0CFG.2_0 =SPIFRS2-SPIFRS0: SPI Frame Size. These three bits determine the number of bits
to shift in/out of the SPI shift register during a data transfer in master mode.
They are ignored in slave mode
=000 1 bits
=001 2 bits
=010 3 bits
=011 4 bits
=100 5 bits
=101 6 bits
=110 7 bits
=111 8 bits
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SPI0CN.7 =SPIF :SPI Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
SPI0CN.6 =WCOL :Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to
the SPI data register was attempted while a data transfer was in progress. It is cleared by software.
SPI0CN.5 =MODF :Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode
collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by
hardware. It must be cleared by software.
SPI0CN.4 =RXOVRN :Receive Overrun Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive buffer
still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
SPI0CN.3 =TXBSY :Transmit Busy Flag.
(R) This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is
cleared by hardware at the end of the transfer.
SPI0CN.2 =SLVSEL :Slave Selected Flag.
(R) This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It
is cleared to logic 0 when NSS is high (slave disabled).
SPI0CN.1 =MSTEN :Master Mode Enable.
=0 :Disable master mode. Operate in slave mode.
=1 :Enable master mode. Operate as a master.
SPI0CN.0 =SPIEN :SPI Enable. This bit enables/disables the SPI.
=0 :SPI disabled.
=1 :SPI enabled
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SPI0CKR.7_0 = SCR7-SCR0 : SPI Clock Rate
These bits determine the frequency of the SCK output when the SPI module is configured
for master mode operation. The SCK clock frequency is a divided down version of the
system clock, and is given in the following equations:
fSCK = 0.5 * fSYSCLK / (SPI0CKR + 1), for 0 <= SPI0CKR <= 255
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SPI0DAT.7_0 = SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI data. Writing data to SPI0DAT
places the data immediately into the shift register and initiates a transfer when in Master
Mode. A read of SPI0DAT returns the contents of the receive buffer.
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PRT0MX.7 =T2EXE : T2EX Enable Bit
=0 : T2EX unavailable at Port pin.
=1 : T2EX routed to Port Pin.
PRT0MX.6 =T2E : T2 Enable Bit
=0 : T2 unavailable at Port pin.
=1 : T2 routed to Port Pin.
PRT0MX.5 =T1E : T1 Enable Bit
=0 : T1 unavailable at Port pin.
=1 : T1 routed to Port Pin.
PRT0MX.4 =T0E : T0 Enable Bit
=0 : T0 unavailable at Port pin.
=1 : T0 routed to Port Pin.
PRT0MX.3 =INT1E : /INT1 Enable Bit
=0 : /INT1 unavailable at Port pin.
=1 : /INT1 routed to port pin.
PRT0MX.2 =INT0E : /INT0 Enable Bit
=0 : /INT0 unavailable at Port pin.
=1 : /INT0 routed to Port Pin.
PRT0MX.1 =UNUSED : Read = 0, Write = don.t care.
PRT0MX.0 =UARTEN : UART I/O Enable
=0 : UART I/O unavailable at port pins.
=1 : TX, RX routed to pins P0.0 and P0.1, respective
--------------------------------------------------------------------------------------
PRT1MX.7 =UNUSED : Read = 0.
PRT1MX.6 =SYSCKE : SYSCLK Output Enable Bit
=0 : SYSCLK unavailable at the port pin.
=1 : SYSCLK output routed to pin P1.6
PRT1MX.5_2 =UNUSED : Read = 0000b, Write = don.t care.
PRT1MX.1 =CP1OEN : Comparator 1 Output Enable bit.
=0 : CP1 unavailable at Port pin.
=1 : CP1 routed to Port Pin P1.5.
PRT1MX.0 =CP0OEN : Comparator 0 Output Enable Bit
=0 : CP0 unavailable at port pin.
=1 : CP0 routed to port pin P1.2.
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PRT2MX.7 =GWPUD : Global Port I/O Weak Pull-up Disable Bit
=0 : Weak Pull-ups Enabled for all ports.
=1 : Weak Pull-ups Disabled (Bits 6-3 Don.t cares)
PRT2MX.6 =P3WPUD : Port 3 Weak Pull-up Disable Bit
=0 : Weak Pull-ups Enabled for port 3
=1 : Weak Pull-ups Disabled for port 3
PRT2MX.5 =P2WPUD : Port 2 Weak Pull-up Disable Bit
=0 : Weak Pull-ups Enabled for port 2.
=1 : Weak Pull-ups Disabled for port 2
PRT2MX.4 =P1WPUD : Port 1 Weak Pull-up Disable Bit
=0 : Weak Pull-ups Enabled for port 1
=1 : Weak Pull-ups Disabled for port 1
PRT2MX.3 =P0WPUD : Port 0 Weak Pull-up Disable Bit
=0 : Weak Pull-ups Enabled for port 0
=1 : Weak Pull-ups Disabled for port 0
PRT2MX.2-1 =UNUSED : Read = 00b, Write = don.t care.
PRT2MX.0 =SPI0OEN : SPI Bus I/O Enable Bit.
=0 : SPI I/O unavailable at port pins.
=1 : SCK, MISO, MOSI, NSS routed to pins P2.0, P2.1, P2.2, and P2.3 respectively
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PRT0CF.7_0 =Output Configuration Bits for P0.7-P0.0 (respectively)
=0 : Corresponding P0.n Output mode is Open-Drain.
=1 : Corresponding P0.n Output mode is Push-Pull.
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PRT1CF.7_0 =Output Configuration Bits for P1.7-P1.0 (respectively)
=0 : Corresponding P1.n Output Mode is Open-Drain.
=1 : Corresponding P1.n Output Mode is Push-Pull.
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PRT2CF.7_0 =Output Configuration Bits for P2.7-P2.0 (respectively)
=0 : Corresponding P2.n Output Mode is Open-Drain.
=1 : Corresponding P2.n Output Mode is Push-Pull
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P0MODE.7_0 =Port0 Digital/Analog Input Mode
=0 :Corresponding Port0 pin Digital Input disabled. (For analog use, i.e., ADC).
=1 :Corresponding Port0 pin Digital Input is enabled
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P1MODE.7_0 =Port1 Digital/Analog Output Mode
=0 : Corresponding Port1 pin Digital Input disabled. (For analog use, i.e., ADC or comparators).
=1 : Corresponding Port1 pin Digital Input is enabled.
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P2MODE.7_0 =Port2 Digital/Analog Output Mode
=0 : Corresponding Port2 pin Digital Input disabled. (For analog use, i.e., ADC).
=1 : Corresponding Port2 pin Digital Input is enabled
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T2CON.7 = TF2 : Timer 2 Overflow Flag.
Set by hardware when Timer 2 overflows from 0xFFFF to 0x0000. When the Timer 2
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2 interrupt
service routine. This bit is not automatically cleared by hardware and must be cleared by
software. TF2 will not be set when RCLK and/or TCLK are logic 1.
T2CON.6 = EXF2 : Timer 2 External Flag
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
2EX input pin and EXEN2 is logic 1. When the Timer 2 interrupt is enabled, setting this
bit causes the CPU to vector to the Timer 2 Interrupt service routine. This bit is not
automatically cleared by hardware and must be cleared by software.
T2CON.5 =RCLK : Receive Clock Flag.
Selects which timer is used for the UART.s receive clock in modes 1 or 3.
=0 : Timer 1 overflows used for receive clock
=1 : Timer 2 overflows used for receive clock.
T2CON.4 =TCLK : Transmit Clock Flag.
Selects which timer is used for the UART.s transmit clock in modes 1 or 3.
=0 : Timer 1 overflows used for transmit clock.
=1 : Timer 2 overflows used for transmit clock.
T2CON.3 =EXEN2 : Timer 2 External Enable.
Enables high-to-low transitions on T2EX to trigger captures or reloads when Timer 2 is not
operating in Baud Rate Generator mode.
=0 : High-to-low transitions on T2EX ignored.
=1 : High-to-low transitions on T2EX cause a capture or reload
T2CON.2 =TR2 : Timer 2 Run Control.
This bit enables/disables Timer 2.
=0 : Timer 2 disabled.
=1 : Timer 2 enabled.
T2CON.1 =C/T2 : Counter/Timer Select.
=0 : Timer Function: Timer 2 incremented by clock defined by T2M (CKCON.5).
=1 : Counter Function: Timer 2 incremented by high-to-low transitions on external input pin P0.6/T2.
T2CON.0 =CP/RL2 : Capture/Reload Select.
This bit selects whether Timer 2 functions in capture or auto-reload mode. EXEN2 must be
logic 1 for high-to-low transitions on T2EX to be recognized and used to trigger captures or
reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function in auto-reload mode.
=0 : Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1).
=1 : Capture on high-to-low transition at T2EX (EXEN2 = 1)
------------------------------------------------------------------------------------
RCAP2L =
Timer 2 Capture Register Low Byte.
The RCAP2L register captures the low byte of Timer 2 when Timer 2 is configured in capture mode.
When Timer 2 is configured in auto-reload mode, it holds the low byte of the reload value.
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