📄 add4.tan.rpt
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Classic Timing Analyzer report for add4
Sun May 13 11:03:57 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 15.741 ns ; a[0] ; s[2] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 15.741 ns ; a[0] ; s[2] ;
; N/A ; None ; 15.369 ns ; ci ; s[2] ;
; N/A ; None ; 15.199 ns ; b[0] ; s[2] ;
; N/A ; None ; 14.940 ns ; a[1] ; s[2] ;
; N/A ; None ; 14.893 ns ; b[1] ; s[2] ;
; N/A ; None ; 14.065 ns ; a[0] ; co ;
; N/A ; None ; 13.994 ns ; a[0] ; s[3] ;
; N/A ; None ; 13.693 ns ; ci ; co ;
; N/A ; None ; 13.622 ns ; ci ; s[3] ;
; N/A ; None ; 13.523 ns ; b[0] ; co ;
; N/A ; None ; 13.452 ns ; b[0] ; s[3] ;
; N/A ; None ; 13.264 ns ; a[1] ; co ;
; N/A ; None ; 13.217 ns ; b[1] ; co ;
; N/A ; None ; 13.193 ns ; a[1] ; s[3] ;
; N/A ; None ; 13.146 ns ; b[1] ; s[3] ;
; N/A ; None ; 12.947 ns ; ci ; s[0] ;
; N/A ; None ; 12.918 ns ; a[0] ; s[0] ;
; N/A ; None ; 12.916 ns ; a[0] ; s[1] ;
; N/A ; None ; 12.544 ns ; ci ; s[1] ;
; N/A ; None ; 12.383 ns ; b[0] ; s[0] ;
; N/A ; None ; 12.374 ns ; b[0] ; s[1] ;
; N/A ; None ; 11.724 ns ; a[1] ; s[1] ;
; N/A ; None ; 11.676 ns ; b[1] ; s[1] ;
; N/A ; None ; 9.966 ns ; b[2] ; s[2] ;
; N/A ; None ; 9.566 ns ; a[2] ; s[2] ;
; N/A ; None ; 8.684 ns ; b[2] ; co ;
; N/A ; None ; 8.613 ns ; b[2] ; s[3] ;
; N/A ; None ; 8.291 ns ; a[2] ; co ;
; N/A ; None ; 8.252 ns ; b[3] ; co ;
; N/A ; None ; 8.220 ns ; a[2] ; s[3] ;
; N/A ; None ; 8.190 ns ; a[3] ; co ;
; N/A ; None ; 7.790 ns ; b[3] ; s[3] ;
; N/A ; None ; 7.727 ns ; a[3] ; s[3] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Sun May 13 11:03:55 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add4 -c add4 --timing_analysis_only
Info: Longest tpd from source pin "a[0]" to destination pin "s[2]" is 15.741 ns
Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 2; PIN Node = 'a[0]'
Info: 2: + IC(6.764 ns) + CELL(0.596 ns) = 8.305 ns; Loc. = LCCOMB_X33_Y8_N16; Fanout = 2; COMB Node = 'Add0~15'
Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.391 ns; Loc. = LCCOMB_X33_Y8_N18; Fanout = 2; COMB Node = 'Add0~17'
Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 8.897 ns; Loc. = LCCOMB_X33_Y8_N20; Fanout = 1; COMB Node = 'Add0~18'
Info: 5: + IC(3.788 ns) + CELL(3.056 ns) = 15.741 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 's[2]'
Info: Total cell delay = 5.189 ns ( 32.96 % )
Info: Total interconnect delay = 10.552 ns ( 67.04 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 103 megabytes of memory during processing
Info: Processing ended: Sun May 13 11:03:57 2007
Info: Elapsed time: 00:00:02
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