decoder2_4.hier_info

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

|decoder2_4
m0 <= 7408:inst2.1
S0 => 7404:inst1.2
S0 => 7408:inst4.3
S0 => 7408:inst5.3
S1 => 7404:inst.2
S1 => 7408:inst3.2
S1 => 7408:inst5.2
m1 <= 7408:inst4.1
m2 <= 7408:inst3.1
m3 <= 7408:inst5.1


|decoder2_4|7408:inst2
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|decoder2_4|7404:inst1
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0


|decoder2_4|7404:inst
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0


|decoder2_4|7408:inst4
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|decoder2_4|7408:inst3
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|decoder2_4|7408:inst5
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1