yuanlitu.map.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "ISGN_ELABORATION_HEADER" "qiankui:114\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"qiankui:114\|lpm_add_sub:Add1\"" {  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "qiankui:114\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"qiankui:114\|lpm_add_sub:Add2\"" {  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "fankui1:113\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\"" {  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fankui1:113\|lpm_add_sub:Add2\|addcore:adder fankui1:113\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\|addcore:adder\", which is child of megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fankui1:113\|lpm_add_sub:Add2 " "Info: Instantiated megafunction \"fankui1:113\|lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 13 " "Info: Parameter \"LPM_WIDTH\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fankui1:113\|lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:oflow_node fankui1:113\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fankui1:113\|lpm_add_sub:Add2 " "Info: Instantiated megafunction \"fankui1:113\|lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 13 " "Info: Parameter \"LPM_WIDTH\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fankui1:113\|lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:result_node fankui1:113\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fankui1:113\|lpm_add_sub:Add2 " "Info: Instantiated megafunction \"fankui1:113\|lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 13 " "Info: Parameter \"LPM_WIDTH\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "fankui1:113\|lpm_add_sub:Add2\|altshift:result_ext_latency_ffs fankui1:113\|lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"fankui1:113\|lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "fankui1:113\|lpm_add_sub:Add2 " "Info: Instantiated megafunction \"fankui1:113\|lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 13 " "Info: Parameter \"LPM_WIDTH\" = \"13\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|yuanlitu\|ad1674ctrl:143\|current_state 5 " "Info: State machine \"\|yuanlitu\|ad1674ctrl:143\|current_state\" contains 5 states" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|yuanlitu\|ad1674ctrl:142\|current_state 5 " "Info: State machine \"\|yuanlitu\|ad1674ctrl:142\|current_state\" contains 5 states" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|yuanlitu\|adc0809ctrl:117\|current_state 7 " "Info: State machine \"\|yuanlitu\|adc0809ctrl:117\|current_state\" contains 7 states" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|yuanlitu\|ad1674ctrl:143\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|yuanlitu\|ad1674ctrl:143\|current_state\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|yuanlitu\|ad1674ctrl:143\|current_state " "Info: Encoding result for state machine \"\|yuanlitu\|ad1674ctrl:143\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad1674ctrl:143\|current_state.st4 " "Info: Encoded state bit \"ad1674ctrl:143\|current_state.st4\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad1674ctrl:143\|current_state.st3 " "Info: Encoded state bit \"ad1674ctrl:143\|current_state.st3\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad1674ctrl:143\|current_state.st2 " "Info: Encoded state bit \"ad1674ctrl:143\|current_state.st2\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad1674ctrl:143\|current_state.st1 " "Info: Encoded state bit \"ad1674ctrl:143\|current_state.st1\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "ad1674ctrl:143\|current_state.st0 " "Info: Encoded state bit \"ad1674ctrl:143\|current_state.st0\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yuanlitu\|ad1674ctrl:143\|current_state.st0 00000 " "Info: State \"\|yuanlitu\|ad1674ctrl:143\|current_state.st0\" uses code string \"00000\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yuanlitu\|ad1674ctrl:143\|current_state.st1 00011 " "Info: State \"\|yuanlitu\|ad1674ctrl:143\|current_state.st1\" uses code string \"00011\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yuanlitu\|ad1674ctrl:143\|current_state.st2 00101 " "Info: State \"\|yuanlitu\|ad1674ctrl:143\|current_state.st2\" uses code string \"00101\"" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%