diff_io_top.map.eqn

altera FPGA/CPLD高级篇(VHDL源代码)

--E1L61 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~LOCKED
--This is a fast PLL. The LOCKED output for a fast PLL is active low and not active high.
E1L61 = PLL.LOCKED(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1L9 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT0
E1L9 = PLL.ENABLE0(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1L01 is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll~ENAOUT1
E1L01 = PLL.ENABLE1(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1_pll is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll
E1_pll = PLL.CLK0(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));

--E1_rx_outclock is lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|rx_outclock
E1_rx_outclock = PLL.CLK2(.ENA(), .COMPARATOR(rx_data_align), .INCLK(rx_inclock));


--F1_tx_out[1] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[1]
F1_tx_out[1]_data_in = DATA(F1_txreg[8], F1_txreg[9], F1_txreg[10], F1_txreg[11], F1_txreg[12], F1_txreg[13], F1_txreg[14], F1_txreg[15]);
F1_tx_out[1] = SERDES_TX.DATAOUT(.CLK0(F1_pll), .ENABLE0(F1L21), F1_tx_out[1]_data_in);


--F1_tx_out[0] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_out[0]
F1_tx_out[0]_data_in = DATA(F1_txreg[0], F1_txreg[1], F1_txreg[2], F1_txreg[3], F1_txreg[4], F1_txreg[5], F1_txreg[6], F1_txreg[7]);
F1_tx_out[0] = SERDES_TX.DATAOUT(.CLK0(F1_pll), .ENABLE0(F1L21), F1_tx_out[0]_data_in);


--F1_tx_outclock is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|tx_outclock
F1_tx_outclock_data_in = DATA(VCC, VCC, GND, GND, GND, GND, VCC, VCC);
F1_tx_outclock = SERDES_TX.DATAOUT(.CLK0(F1L4), .ENABLE0(F1L21), F1_tx_outclock_data_in);


--F1L21 is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|pll~ENAOUT1
F1L21 = PLL.ENABLE1(.ENA(), .COMPARATOR(), .INCLK(E1_rx_outclock));

--F1_pll is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|pll
F1_pll = PLL.CLK0(.ENA(), .COMPARATOR(), .INCLK(E1_rx_outclock));

--F1L4 is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|pll~CLK1
F1L4 = PLL.CLK1(.ENA(), .COMPARATOR(), .INCLK(E1_rx_outclock));


--F1_txreg[8] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[8]
--operation mode is normal

F1_txreg[8]_lut_out = H1_result[8];
F1_txreg[8] = DFFEA(F1_txreg[8]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[9] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[9]
--operation mode is normal

F1_txreg[9]_lut_out = H1_result[9];
F1_txreg[9] = DFFEA(F1_txreg[9]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[10] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[10]
--operation mode is normal

F1_txreg[10]_lut_out = H1_result[10];
F1_txreg[10] = DFFEA(F1_txreg[10]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[11] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[11]
--operation mode is normal

F1_txreg[11]_lut_out = H1_result[11];
F1_txreg[11] = DFFEA(F1_txreg[11]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[12] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[12]
--operation mode is normal

F1_txreg[12]_lut_out = H1_result[12];
F1_txreg[12] = DFFEA(F1_txreg[12]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[13] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[13]
--operation mode is normal

F1_txreg[13]_lut_out = H1_result[13];
F1_txreg[13] = DFFEA(F1_txreg[13]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[14] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[14]
--operation mode is normal

F1_txreg[14]_lut_out = H1_result[14];
F1_txreg[14] = DFFEA(F1_txreg[14]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[15] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[15]
--operation mode is normal

F1_txreg[15]_lut_out = H1_result[15];
F1_txreg[15] = DFFEA(F1_txreg[15]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[0] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[0]
--operation mode is normal

F1_txreg[0]_lut_out = H1_result[0];
F1_txreg[0] = DFFEA(F1_txreg[0]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[1] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[1]
--operation mode is normal

F1_txreg[1]_lut_out = H1_result[1];
F1_txreg[1] = DFFEA(F1_txreg[1]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[2] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[2]
--operation mode is normal

F1_txreg[2]_lut_out = H1_result[2];
F1_txreg[2] = DFFEA(F1_txreg[2]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[3] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[3]
--operation mode is normal

F1_txreg[3]_lut_out = H1_result[3];
F1_txreg[3] = DFFEA(F1_txreg[3]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[4] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[4]
--operation mode is normal

F1_txreg[4]_lut_out = H1_result[4];
F1_txreg[4] = DFFEA(F1_txreg[4]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[5] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[5]
--operation mode is normal

F1_txreg[5]_lut_out = H1_result[5];
F1_txreg[5] = DFFEA(F1_txreg[5]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[6] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[6]
--operation mode is normal

F1_txreg[6]_lut_out = H1_result[6];
F1_txreg[6] = DFFEA(F1_txreg[6]_lut_out, E1_rx_outclock, VCC, , , , );


--F1_txreg[7] is lvds_tx:lvds_tx_inst|altlvds_tx:altlvds_tx_component|txreg[7]
--operation mode is normal

F1_txreg[7]_lut_out = H1_result[7];
F1_txreg[7] = DFFEA(F1_txreg[7]_lut_out, E1_rx_outclock, VCC, , , , );


--H1_result[0] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (9-bit)
H1_result[0] = H1_mac_mult1;

--H1_result[1] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[1]
H1_result[1] = H1L2Q;

--H1_result[2] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[2]
H1_result[2] = H1L3Q;

--H1_result[3] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[3]
H1_result[3] = H1L4Q;

--H1_result[4] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[4]
H1_result[4] = H1L5Q;

--H1_result[5] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[5]
H1_result[5] = H1L6Q;

--H1_result[6] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[6]
H1_result[6] = H1L7Q;

--H1_result[7] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[7]
H1_result[7] = H1L8Q;

--H1_result[8] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[8]
H1_result[8] = H1L9Q;

--H1_result[9] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[9]
H1_result[9] = H1L01Q;

--H1_result[10] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[10]
H1_result[10] = H1L11Q;

--H1_result[11] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[11]
H1_result[11] = H1L21Q;

--H1_result[12] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[12]
H1_result[12] = H1L31Q;

--H1_result[13] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[13]
H1_result[13] = H1L41Q;

--H1_result[14] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[14]
H1_result[14] = H1L51Q;

--H1_result[15] is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|result[15]
H1_result[15] = H1L61Q;


--H1_mac_mult1 is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1
--DSP Block Multiplier Base Width: 9-bits
H1_mac_mult1_a_data = DATA(E1_rxreg[7], E1_rxreg[6], E1_rxreg[5], E1_rxreg[4], E1_rxreg[3], E1_rxreg[2], E1_rxreg[1], E1_rxreg[0]);
H1_mac_mult1_a_reg = DFFE(H1_mac_mult1_a_data, E1_rx_outclock, , , );
H1_mac_mult1_a_rep = UNSIGNED(H1_mac_mult1_a_reg);
H1_mac_mult1_b_data = DATA(E1_rxreg[15], E1_rxreg[14], E1_rxreg[13], E1_rxreg[12], E1_rxreg[11], E1_rxreg[10], E1_rxreg[9], E1_rxreg[8]);
H1_mac_mult1_b_reg = DFFE(H1_mac_mult1_b_data, E1_rx_outclock, , , );
H1_mac_mult1_b_rep = UNSIGNED(H1_mac_mult1_b_reg);
H1_mac_mult1_result = H1_mac_mult1_a_rep * H1_mac_mult1_b_rep;
H1_mac_mult1_result_reg = DFFE(H1_mac_mult1_result, E1_rx_outclock, , , );
H1_mac_mult1 = H1_mac_mult1_result_reg[0];

--H1L2Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT1
H1L2Q = H1_mac_mult1_result_reg[1];

--H1L3Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT2
H1L3Q = H1_mac_mult1_result_reg[2];

--H1L4Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT3
H1L4Q = H1_mac_mult1_result_reg[3];

--H1L5Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT4
H1L5Q = H1_mac_mult1_result_reg[4];

--H1L6Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT5
H1L6Q = H1_mac_mult1_result_reg[5];

--H1L7Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT6
H1L7Q = H1_mac_mult1_result_reg[6];

--H1L8Q is mult:mult_inst|altmult_add:ALTMULT_ADD_component|mult_add_v4n1:auto_generated|mac_mult1~DATAOUT7
H1L8Q = H1_mac_mult1_result_reg[7];